2 bit multiplier

[xiibweb]

Hi,

I hv tried to run the following 2bit multiplier vhdl code in xilinx...
and getting following error...

HDLParsers:164 - "C:/Projects/knm/2bit.vhd" Line 11. parse error,
unexpected INTEGER_LITERAL, expecting IDENTIFIER

I am just a beginner any1 kindly help....

thnx

John

here is the code...

**********************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity 2bit is
Port ( A0 : in std_logic_vector(1 downto 0);
A1 : in std_logic_vector(1 downto 0);
B0 : in std_logic_vector(1 downto 0);
B1 : in std_logic_vector(1 downto 0);
B2 : in std_logic_vector(3 downto 0);
C0 : out std_logic_vector(3 downto 0);
C1 : out std_logic_vector(3 downto 0);
C2 : out std_logic_vector(3 downto 0);
C3 : out std_logic_vector(3 downto 0));
end 2bit;

architecture Behavioral of 2bit is

begin
C0 <= A0 and B0;

C1 <= (A0 and not A1 and B1) or
(A0 and not B0 and B1) or
(not A0 and A1 and B0) or
(A1 and B0 and not B1);

C2 <= (A1 and B1 and not B0) or
(A1 and not A0 and B1);

C3 <= A1 and A0 and B1 and B0;

end Behavioral;

**********************************************************

 

[Paul Uiterlinden]

HDLParsers:164 - "C:/Projects/knm/2bit.vhd" Line 11. parse error,
unexpected INTEGER_LITERAL, expecting IDENTIFIER

entity 2bit is

Names of identifiers should not start with a digit. Choose two_bit, or
something similar instead.

Paul.

 

[charles.elias]

try:
-----------------------------------------------------------------------------
entity 2bit is
port( A : in std_logic_vector( 1 downto 0 );
B : in std_logic_vector( 1 downto 0 );
C : out std_logic_vector( 3 downto 0 )
);

architecture Behavioral of 2bit is

begin
C( 0 ) <= A( 0 ) and B( 0 );

C( 1 ) <= (A( 0 ) and not A( 1 ) and B( 1 )) or
(A( 0 ) and not B( 0 ) and B( 1 )) or
(not A( 0 ) and A( 1 ) and B( 0 )) or
(A( 1 ) and B( 0 ) and not B( 1 ));


C( 2 ) <= (A( 1 ) and B( 1 ) and not B( 0 )) or
(A( 1 ) and not A( 0 ) and B( 1 ));


C3 <= A( 1 )and A( 0 ) and B( 1 ) and B( 0 );


end Behavioral;
----------------------------------------------------------------------------------------------
Please note that I have corrected the syntax, but have left the basic
logic as is. It should compile now, but whether it gives the correct
result is up to you. Your basic error is that you must refer to the
elements of a vector as I have shown. Also you have overspecified your
port. You need only 3 vectors.

 

[charles.elias]

Paul is right, I missed the "2bit" naming error. My corrected reply
follows:

(e-mail address removed) Apr 12, 6:01 am show options

Newsgroups: comp.lang.vhdl
From: (e-mail address removed) - Find messages by this author
Date: 12 Apr 2005 06:01:40 -0700
Local: Tues,Apr 12 2005 6:01 am
Subject: Re: 2 bit multiplier
Reply | Reply to Author | Forward | Print | Individual Message | Show
original | Remove | Report Abuse

try:
------------------------------­------------------------------­-----------------

entity two_bit is
port( A : in std_logic_vector( 1 downto 0 );
B : in std_logic_vector( 1 downto 0 );
C : out std_logic_vector( 3 downto 0 )
);


architecture Behavioral of two_bit is


begin
C( 0 ) <= A( 0 ) and B( 0 );


C( 1 ) <= (A( 0 ) and not A( 1 ) and B( 1 )) or
(A( 0 ) and not B( 0 ) and B( 1 )) or
(not A( 0 ) and A( 1 ) and B( 0 )) or
(A( 1 ) and B( 0 ) and not B( 1 ));


C( 2 ) <= (A( 1 ) and B( 1 ) and not B( 0 )) or
(A( 1 ) and not A( 0 ) and B( 1 ));


C3 <= A( 1 )and A( 0 ) and B( 1 ) and B( 0 );


end Behavioral;
------------------------------­------------------------------­------------------------------­----

Please note that I have corrected the syntax, but have left the basic
logic as is. It should compile now, but whether it gives the correct
result is up to you. Your basic error is that you must refer to the
elements of a vector as I have shown. Also you have overspecified your

port. You need only 3 vectors.

 

[xiibweb]

thnx people.. i appreciate for the help... paul was right... i hv just
changed to twobit now code is working fine...

thanx again

regards
john

 

[kiran423]

Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity topmodule is
Port (
Clk : in std_logic;
Uartout : out std_logic; -----9600
Uartout2: out std_logic; ------4800
Uartout3: out std_logic ;-----2400//;
);
End topmodule;

Architecture beav of topmodule is
Constant system_speed: natural: = 50e6;
Signal clk1: std_logic;
Signal clk_s: std_logic;
Signal clk_s1: std_logic;
Signal uartout: std_logic;

Component uart1
Generic (system_speed: natural: = 50e6; integer);// Generic (system_speed: natural: = 50e6; integer);
Port (clock: in std_logic;
Txd: out std_logic);
End component;
Begin
P1: process (clk)
Begin
If (clk'event and clk = '1') then
Clk_s <= not (clk_s);
End if;
End process P1;

P2: process (clk)
Begin
If (clk_s'event and clk_s = '1') then
Clk_s1 <= not (clk_s1);
End if;
End process P2;

Clock_mana1: uart1 generic map (system_speed=> speed)
Port map (clk, uartout);
Clock_mana2: uart1 generic map (system_speed=> speed)
Port map (clk_s, uartout2);
Clock_mana3: uart1 generic map (system_speed=> speed)
Port map (clk_s1, uartout3);
End beav;





iam getting error as
Line 29. parse error, unexpected CLOSEPAR, expecting IDENTIFIER

on the code
);
end topmodule please help me

 

[sergio]

Hi, in the first description, how do I get the functions