2 flip-flop synchronizer

[andys86498]

hello , i have some problems about 2 ff synchronizer vhdl structure

here is the cdl code of a synchronizer module from website

https://github.com/Nuand/bladeRF/blob/master/hdl/fpga/ip/nuand/synthesis/synchronizer.vhd
===================
library ieee ;
use ieee.std_logic_1164.all ;
entity synchronizer is
generic (
RESET_LEVEL : std_logic := '1'
) ;
port (
reset : in std_logic ;
clock : in std_logic ;
async : in std_logic ;
sync : out std_logic
) ;
end entity ;
architecture arch of synchronizer is
begin
synchronize : process( clock, reset )
variable reg0, reg1 : std_logic ;
begin
if( reset = '1' ) then
sync <= RESET_LEVEL ;
reg0 := RESET_LEVEL ;
reg1 := RESET_LEVEL ;
elsif( rising_edge( clock ) ) then
sync <= reg1 ;
reg1 := reg0 ;
reg0 := async ;
end if ;
end process ;
end architecture ;

=======


i want to ask why the red lines use ":= " rather than "<="

i have studied vhdl code book and 2 ff synchronizer structure

i know that := means no delay assignment

but in 2 ff synchronizer structure there are indeed 2 register exist

thanks everyone

 

[netguy63]

<= are for signals
:= are for variables

Tom