2's compliment+parity+parallel to serial help please...

[axeman0226]

Hello everyone! I'm a total newb/rookie to VHDL but would like to start using it for logic design in FPGA's. I have some digital design experience and some programming experience, so I'm hoping the learning curve won't be too bad(?).

I have a seemingly simple project to learn with, but need some help with starting out & implementing it please.

The crux of the problem: I need to read in a 16-bit wide (parallel) word, convert it to an 18-bit word by tacking on a '0' as a placeholder along with a parity bit, also compute the 2's compliment of the word and convert it to an 18-bit word in the same manner ('0' placeholder along with a parity bit), and send the 2 18-bit words out serially along with a clock (clock must have rising & falling edges while a data bit is valid).

I was thinking of calculating the parity bit in the usual cascade manner (not sure of there's a better way):

int1 <= din(0) xor din(1);
int2 <= int1 xor din(2);
int3 <= int2 xor din(3);
int4 <= int3 xor din(4);
int5 <= int4 xor din(5);
int6 <= int5 xor din(6);
int7 <= int6 xor din(7);
int8 <= int7 xor din(8);
int9 <= int8 xor din(9);
int10 <= int9 xor din(10);
int11 <= int10 xor din(11);
int12 <= int11 xor din(12);
int13 <= int12 xor din(13);
int14 <= int13 xor din(14);
parity <= int14 xor din(15);

and the 2's compliment is as simple as(?):

twos_comp <= not(din)+1;

I'm not sure how I'd go about implementing the parallel to serial conversion (along with clock) or how to put everything together.

Anyone out there willing to help educate me? Any help getting me going on this would be truly appreciated!!!

Also, I'd like to order a couple VHDL books for reference and was looking at: Circuit Design with VHDL by Pedroni and FPGA Prototyping by VHDL Examples by Chu. Yea/nea or any other recommendations?

Thanks again!!!