Sorry, yes, I had confused myself by thinking about PAE. For normal
32bit systems this is true.
it is also true of systems using PAE.
there is a way to get around the 3GB limit though, but it actually
involves a different strategy:
swapping out the page tables on transitions to/from kernel space.
big downside: this is kind of slow...
However, the OP is using a PAE kernel. That should theoretically allow a
per-process limit of 4GB. I've never had the chance to use PAE kernels
on PAE supported hardware, but IIRC that's what PAE is for, isn't it?
no, PAE does not expand the size of the virtual address space, only the
physical address space (mostly via making page-table entries bigger, and
adding another page-table level):
4kB / 8 = 512 (2^9)
9*3 + 12 = 39
but, the top-level is only partially filled (4 entries), so:
9+9+2 + 12 = 32
vs (non-PAE):
4kB / 4 = 1024 (2^10)
10+10 + 12 = 32
the reason for expanding the page-table entry size is mostly so that
they can refer to more pages (more bits allowing a larger physical
address space).
it means essentially that you can have 36-bits (or more) for the
physical RAM, but still only 4GB per-process (apart from using ugly
bank-switching nastiness).
given that the kernel still needs to map into a 4GB space, there is
little change from before (leaving a full 4GB for the app requiring an
address-space switch).
PAE is partly involved in x86-64 though.
more levels of page-tables may be used:
4kB / 8 = 512 (2^9)
9*4 + 12 = 48
9*5 + 12 = 57
note that the size of the external (physical) address bus is independent
of the size of the supported virtual address space, and depends some on
the processor.
note that, while 64 bit page-table entries would theoretically allow up
to a full 64 bit physical address... AMD shaved off some of the
high-order bits for use for more flags (like the NX bit). hence, there
is currently a limit here of 56 bits.
not like we will likely be seeing this much RAM anywhere in the near
future though...
