I'm working on sobel edge detection on an fpga using a 3x3 mask. To store the pixel values of the input image, I've decided to use an array. I wrote the code for just the array and some test code to see how it's working. The code worked, so I tried adding a "full" bit that would say when to stop loading the memory. For some reason, whenever I use the "full" bit and implement it to prevent the array from loading again once it's full, the array won't load at all and I get no output. The code is pretty simple and it seems like adding the full bit shouldn't be an issue. Does anyone have any suggestions on what I might be doing wrong?
And the code:
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
entity sobel is
PORT ( input: IN integer:=0;
SW: IN integer:=0;
output: OUT integer:=0;
LEDR: OUT integer:=0;
LEDG: OUT std_logic_vector(8 DOWNTO 0);
CLOCK_50: IN std_logic);
end sobel;
architecture sobelizer of sobel is
constant num_cols: Natural:=640;
constant num_rows: Natural:=480;
constant edge: Natural:=0;
constant foreground: Natural:=255;
constant threshold: Natural:=68;
subtype pixel is integer;
signal full: std_logic:='0';
type memory_array is array (1 to 3, 1 to num_cols) of pixel;
type mask is array (1 to 3, 1 to 3) of pixel;
type next3 is array (1 to 3) of pixel;
begin
process
variable A : mask:=((0,0,0),(0,0,0),(0,0,0));
variable X1 : Natural:=1;
variable Y1 : Natural:=1;
variable Current_X: Integer:=1;
variable Current_Y: Integer:=1;
variable memory: memory_array;
begin
Wait Until CLOCK_50'EVENT and CLOCK_50='1';
if full='0' then
memory(X1,Y1):=input;
X1:=X1+1;
Current_X:=X1;
CUrrent_Y:=Y1
if X1=num_cols+1 then
X1:=1;
Y1:=Y1+1;
current_Y:=Y1;
end if;
if (current_X=num_cols) and (current_Y=num_rows) then
full<='1';
X1:=0;
Y1:=0;
end if;
elsif full='1' then
X1:=0;
Y1:=0;
end if;
end process;
end sobelizer;
And the code:
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
entity sobel is
PORT ( input: IN integer:=0;
SW: IN integer:=0;
output: OUT integer:=0;
LEDR: OUT integer:=0;
LEDG: OUT std_logic_vector(8 DOWNTO 0);
CLOCK_50: IN std_logic);
end sobel;
architecture sobelizer of sobel is
constant num_cols: Natural:=640;
constant num_rows: Natural:=480;
constant edge: Natural:=0;
constant foreground: Natural:=255;
constant threshold: Natural:=68;
subtype pixel is integer;
signal full: std_logic:='0';
type memory_array is array (1 to 3, 1 to num_cols) of pixel;
type mask is array (1 to 3, 1 to 3) of pixel;
type next3 is array (1 to 3) of pixel;
begin
process
variable A : mask:=((0,0,0),(0,0,0),(0,0,0));
variable X1 : Natural:=1;
variable Y1 : Natural:=1;
variable Current_X: Integer:=1;
variable Current_Y: Integer:=1;
variable memory: memory_array;
begin
Wait Until CLOCK_50'EVENT and CLOCK_50='1';
if full='0' then
memory(X1,Y1):=input;
X1:=X1+1;
Current_X:=X1;
CUrrent_Y:=Y1
if X1=num_cols+1 then
X1:=1;
Y1:=Y1+1;
current_Y:=Y1;
end if;
if (current_X=num_cols) and (current_Y=num_rows) then
full<='1';
X1:=0;
Y1:=0;
end if;
elsif full='1' then
X1:=0;
Y1:=0;
end if;
end process;
end sobelizer;
Last edited: