4 bit two flipflop sychronizer

[Bhakti Dedhia]

Hi i have written the code for 4bit two flip flop synchronizer in verilog.can anyone help in generating the est bench for the same.This code is used for detecting clocking issues like metastability when the clock are operating in different clock domains
`timescale 1ns / 1ps
module dff1(data1,clk1,reset1,q1); //Declaration of module ports name
input [3:0] data1; // Assigninf the ports as i/o ports
input clk1, reset1 ;
output reg [3:0] q1;
initial //initialization of port
q1= 4'h0; // Declaration of port as a register to store the value
always @ ( posedge clk1) // positive edge triggering
if (reset1) begin // reset condition
q1 = 4'h0;
end
else
begin
q1 = data1;
#5; //5ns delay
q1 = 4'h0;
end
endmodule

module ff_syn(d,q,clk1,clk2,rst);
input clk1,clk2,rst;
input [3:0] d;
output [3:0] q;
wire [3:0] w1,w2; //according to diagram only q3 is the output. if these are also the output just write
'output' b4 wire
dff1 f1 (.data1(d), .clk1(clk1),.q1(w1),.reset1(rst));
dff1 f2 (.data1(w1),.clk1(clk2),.q1(w2),.reset1(rst)); // hierarchy module structure
dff1 f3 (.data1(w2),.clk1(clk2),.q1(q), .reset1(rst));
endmodule