a Sample and hold circuit model

[Manivannan]

Hi,

i am trying to model a Sample and hold device for a ADC, using
VHDL-AMS on Cadence.I used the Zero Order Hold attribute ('zoh()) to
sample the inputs. The code had no problems running on Mentor Graphics
System Vision, but when i ported the code to Cadence it did not. I
seems that the 'zoh() function is not yet built into Cadence VHDL-AMS
Simulator.
Now my question is that is there any equivalent function for 'zoh() ?

I have posted this query in comp.lang.cad.Cadence , but no reply as of
now!

will be happy if somebody could clear this..

Cheers
Manivannan

 

[cdbular]

I had the same problem. To addres the problem I decided to make a ZOH block.

I made the code using quantity inputs and outputs. The code was tested unsign a sinuosidal signal and it worked fine.

--- CODE OF ZOH BLOCK
library IEEE;                
use IEEE.MATH_REAL.all;
USE IEEE.STD_LOGIC_1164.ALL;        
                     
USE IEEE.ELECTRICAL_SYSTEM.ALL;          

ENTITY ZOHF IS                                    
	GENERIC (Ts: TIME:= 10 us);                                       
	PORT(signal clkout : out bit;
		 QUANTITY Vin : IN REAL:=0.0;                    
		 QUANTITY Vout: OUT REAL:=0.0);
END ZOHF;                                                                      
             
                                                                  
ARCHITECTURE behavior_sampler OF ZOHF IS                                                                                        
    shared variable Vin_HOLD : REAL:=0.0;
	SIGNAL clk: bit :='1';                                                
BEGIN                                                                                    
clock: process (clk)                                                                         
    BEGIN                                                     
        clk <= not clk after Ts/2;             
     END PROCESS clock;                                   
     
samp:PROCESS (clk)               
     BEGIN                                                                                                             
        IF (clk'EVENT AND clk='1') THEN              
        Vin_HOLD:= vin;
        END IF;                                     
    END PROCESS samp;                        
Vout==Vin_HOLD;                                     
clkout<=clk;                               
END behavior_sampler;

The testbench

--Testbench                                                                       
                
LIBRARY DISCIPLINES, IEEE;                               
    USE DISCIPLINES.ELECTROMAGNETIC_SYSTEM.ALL;
    USE IEEE.MATH_REAL.ALL;    
	USE IEEE.STD_LOGIC_1164.ALL;   
                                                
ENTITY bench IS END ENTITY bench;                
                                                                                                               
ARCHITECTURE sample OF bench IS                                           
                                                                                                       
    QUANTITY vin1, n2 : REAL:=0.0;                                                         
	CONSTANT f   : REAL := 1.0E3;
	signal clk : bit;        
                                                                         
BEGIN                                            
                                                                       
     vin1 == 2.0;                                           
ZOH1: ENTITY ZOHF(behavior_sampler)                                
       GENERIC MAP (Ts => 0.05e-3 sec)                 
       PORT MAP (clk,Vin1, n2);                   
END ARCHITECTURE sample;

I hope that will help you