a small vhdl problem

[s_hlu]

Hallo,
I am new to vhdl, now met a problem and dont know how to solve..:stupido:
I am implementing somelike Bitwise Arbitration in can bus, now on my bus interface i have 2 ports, txd_o and rxd_i.(one for transmit, one for receive).
Now i wanna do something like : if(txd_o /= rxd_i) , then sth bla bla.. ----------Now so the problem is obviously that, synthesis says, Object txd_o of mode OUT cannot be read :-(
So does anyone know, how to solve this ? Or has some more better ideas to implement this ? (Bitwise Arbitration need to compare the value this node sent and the value this node read )
Thanks a lot !

Regards,

 

[jeppe]

Try to change OUT with INOUT - this will normally solve the problem