S
Suraj Kurapati
Ruby-VPI is a Ruby interface to IEEE 1364-2005 Verilog VPI.
It lets you create complex Verilog test benches easily and
wholly in Ruby.
• http://ruby-vpi.rubyforge.org
â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”
Version 15.0.0 (2007-01-13)
Summary
This release fixes a problem with compilation of the C
extension, and makes clock generation code correctly affect
Ruby prototypes.
Acknowledgment
Thanks to Derek Graham for reporting the problem with
compilation of the C extension.
Notice
• The Vpi::advance_time method (instead of the
Vpi::simulate method) now invokes the design’s
simulate! method when prototyping is enabled.
This makes clock generation code (passed to the
RubyVpi::init_bench method) affect Ruby prototypes,
just as it affects a real Verilog design.
As a result, Ruby prototypes may need to check for
edge-triggering through the new Vpi::Handle.posedge?
and Vpi::Handle.negedge? methods. For example, see the
new implementation of the Counter prototype.
New features
• Added Vpi::Handle.posedge? and Vpi::Handle.negedge?
methods which check if a handle’s logic value is
currently at a positive or negative edge, respectively.
• Added Vpi::S_vpi_time.integer and
Vpi::S_vpi_time.integer= methods which access the high
and low integer fields as a single 64-bit integer.
• Added utility methods for accessing the value field in
the Vpi::S_vpi_value structure.
Details
• Fixed problem with incorrect Ruby library flag in ext/
extconf.rb. It happens that the mkmf library determines
the correct library flag all by itself!
• Added new prototyping section to user manual.
• Fixed some broken URLs in user documentation.
It lets you create complex Verilog test benches easily and
wholly in Ruby.
• http://ruby-vpi.rubyforge.org
â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”
Version 15.0.0 (2007-01-13)
Summary
This release fixes a problem with compilation of the C
extension, and makes clock generation code correctly affect
Ruby prototypes.
Acknowledgment
Thanks to Derek Graham for reporting the problem with
compilation of the C extension.
Notice
• The Vpi::advance_time method (instead of the
Vpi::simulate method) now invokes the design’s
simulate! method when prototyping is enabled.
This makes clock generation code (passed to the
RubyVpi::init_bench method) affect Ruby prototypes,
just as it affects a real Verilog design.
As a result, Ruby prototypes may need to check for
edge-triggering through the new Vpi::Handle.posedge?
and Vpi::Handle.negedge? methods. For example, see the
new implementation of the Counter prototype.
New features
• Added Vpi::Handle.posedge? and Vpi::Handle.negedge?
methods which check if a handle’s logic value is
currently at a positive or negative edge, respectively.
• Added Vpi::S_vpi_time.integer and
Vpi::S_vpi_time.integer= methods which access the high
and low integer fields as a single 64-bit integer.
• Added utility methods for accessing the value field in
the Vpi::S_vpi_value structure.
Details
• Fixed problem with incorrect Ruby library flag in ext/
extconf.rb. It happens that the mkmf library determines
the correct library flag all by itself!
• Added new prototyping section to user manual.
• Fixed some broken URLs in user documentation.