S
Suraj Kurapati
Ruby-VPI is a Ruby interface to IEEE 1364-2005 Verilog VPI
and a platform for unit testing, rapid prototyping, and
systems integration of Verilog modules through Ruby. It
lets you create complex Verilog test benches easily and
wholly in Ruby.
• See http://ruby-vpi.rubyforge.org for details.
â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”
Project News
The web-based forums[1] have been replaced with a mailing
list[2] that has its own web-based interface[3] if you prefer.
[1] http://rubyforge.org/forum/?group_id=1339
[2] http://ruby-vpi.rubyforge.org/mail/
[3] http://ruby-vpi.rubyforge.org/forum/
â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”
Version 18.0.1 (2007-08-02)
This release fixes some bugs regarding simulation time and
control.
Thanks
• Calvin Wong reported the bugs listed in the Repairs
section.
Repairs
• VCS does not acknowledge passage of time when
cbReadWriteSynch callback is used, so I reverted back
to using the cbAfterDelay callback (as was done in
version 17.0.0).
• Ruby-VPI did not give control back to the Verilog
simulator before it exited. As a result, the Verilog
simulator did not have a chance to do any clean up or
finish any pending tasks that remained in the
simulation.
and a platform for unit testing, rapid prototyping, and
systems integration of Verilog modules through Ruby. It
lets you create complex Verilog test benches easily and
wholly in Ruby.
• See http://ruby-vpi.rubyforge.org for details.
â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”
Project News
The web-based forums[1] have been replaced with a mailing
list[2] that has its own web-based interface[3] if you prefer.
[1] http://rubyforge.org/forum/?group_id=1339
[2] http://ruby-vpi.rubyforge.org/mail/
[3] http://ruby-vpi.rubyforge.org/forum/
â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”â”
Version 18.0.1 (2007-08-02)
This release fixes some bugs regarding simulation time and
control.
Thanks
• Calvin Wong reported the bugs listed in the Repairs
section.
Repairs
• VCS does not acknowledge passage of time when
cbReadWriteSynch callback is used, so I reverted back
to using the cbAfterDelay callback (as was done in
version 17.0.0).
• Ruby-VPI did not give control back to the Verilog
simulator before it exited. As a result, the Verilog
simulator did not have a chance to do any clean up or
finish any pending tasks that remained in the
simulation.