Any body can explain whats wrong with this simple code ERROR:Xst:827

[chanson]

process (clk, rst)
begin
if rst'event and rst = '0' then
Q <='0';
elsif clk = '1' then
Q<=D
end process.


it doesnt seem voilate the rules:

The synchronous element description is based on the 'event VHDL attribute. In order for XST to infer a synchronous element, the 'event VHDL attribute must be present in the topmost "IF" statement of your process. Furthermore, there should be no embedded 'event statements within a process.

but how come XST doesnt allow to monitor the rst falling edge triger. it gave me error : ERROR:Xst:827

I modify the code like the following and it works. anybody can explain?

process (clk, rst)
begin
if rst = '0' then
Q <='0';
elsif clk'event and clk = '1' then
Q<=D
end process.

 

[chanson]

anybody help pls?

 

[jeppe]

If your expect a VHDL code to be executed as a "normal" software program would both "programs" be ok.

However will your VHDL be synthesized into hardware - and you can't have a F/F which react at a rising_edge and does some ELSE when no rising_edge.

Jeppe