Arrays in Port

[mirendil]

Hi,
I want to include an unconstrained array in my port declaration, instead of declaring n time std_logic_vector (that would be much easier to use!)

entity Window is
generic (n:integer:=3;--nombre de cartes
p:integer:=3 --Position de la carte
);
Port (
CLK, HS, VS: in std_logic;
WDO: out std_logic;
LenghH: in array16_type;
LenghV: in array16_type;
StartH: in array16_type;
StartV: in array16_type;
TabZorder: in array5_type;
Poscarte: in std_logic_vector(4 downto 0)
);
end Window;

architecture Behav of Window is
type array16_type is Array (0 to n-1) of std_logic_vector(15 downto 0);
type array5_type is Array (0 to n-1) of std_logic_vector(4 downto 0);
type BusWD_type is Array (0 to n-1) of std_logic;
type orout_type is Array (0 to n) of std_logic;

...

I read on a forum that it could work like this, but it generates errors while compiling (using Modelsim) :
"** Error: D:/Jerome Kusseling/Invg23/VHDL/Window/Window.vhd(27): Unknown identifier 'array16_type'.
** Error: D:/Jerome Kusseling/Invg23/VHDL/Window/Window.vhd(28): Unknown identifier 'array16_type'.
** Error: D:/Jerome Kusseling/Invg23/VHDL/Window/Window.vhd(29): Unknown identifier 'array16_type'.
** Error: D:/Jerome Kusseling/Invg23/VHDL/Window/Window.vhd(30): Unknown identifier 'array16_type'.
** Error: D:/Jerome Kusseling/Invg23/VHDL/Window/Window.vhd(31): Unknown identifier 'array5_type'.

any help ?