L
Lore Leunoeg
Hello
I need to write a testbench which assigns one value at the rising edge and
another value at the falling edge of the clock.
I tried the code below but the value is always assignd only at the rising
edge. What is my mistake?
Thank you
Sincerely
Lore
....
blabla: process
variable i : integer;
begin
s_clk <= '0';
s_reset <= '0';
s_reset <= '1';
while i<50 loop
s_din <= std_logic_vector(to_unsigned(i,width)); -- integer nach
std_logic vector
s_clk <= '1';
wait for 50 ns;
i:= i + 1;
s_din <= std_logic_vector(to_unsigned(i,width)); -- integer nach
std_logic vector
s_clk <= '0';
wait for 50 ns;
end loop;
end process;
....
I need to write a testbench which assigns one value at the rising edge and
another value at the falling edge of the clock.
I tried the code below but the value is always assignd only at the rising
edge. What is my mistake?
Thank you
Sincerely
Lore
....
blabla: process
variable i : integer;
begin
s_clk <= '0';
s_reset <= '0';
s_reset <= '1';
while i<50 loop
s_din <= std_logic_vector(to_unsigned(i,width)); -- integer nach
std_logic vector
s_clk <= '1';
wait for 50 ns;
i:= i + 1;
s_din <= std_logic_vector(to_unsigned(i,width)); -- integer nach
std_logic vector
s_clk <= '0';
wait for 50 ns;
end loop;
end process;
....