Assigning arrays of different types

[ALuPin]

Hi,

I am trying the following:


library ieee;
use ieee.std_logic_1164.all;

entity test is
end test;

architecture rtl of test is

subtype stype_2b is std_logic_vector(1 downto 0);
type type_ch_array is array (natural range <>) of stype_2b;
type type_ch is array (natural range <>) of stype_2b;


signal ls_array : type_ch_array(15 downto 0);

signal ls_subarray : type_ch(3 downto 0);

begin

ls_array(3 downto 0) <= ls_subarray;

end rtl;

Can someone explain why the compiler complains about
that assignment ?

Rgds

 

[ALuPin]

Thank you, the explanation is very clear.

Best regards