assigning different elements of array

[Hemang]

Hi,

I have an small test case below.. This code when simulated with
modelsim v6.4b or d (haven't tried other simulators) give me U on all
the data_delay array elements and also on the dout port. If I move the
data_delay(0) assignment to be within the same process (as shown in
the commented code in the architecture), it starts to work..

I was wondering if VHDL LRM stipulates ALL elements of an array to be
assigned within the same "scope", or is this a bug in modelsim?

-------- Code begins ------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dut is
port (
data : in std_logic_vector(15 downto 0) := X"0030";
dout : out std_logic_vector(15 downto 0)
);
end dut;

architecture behav of dut is

type array_data_term is array (0 to 7) of std_logic_vector(15 downto
0);
signal data_delay : array_data_term;

signal clk : std_logic;
constant C_CLK_PERIOD : time := 5 ns;

begin

clk_gen: process
begin
clk <= '0';
wait for C_CLK_PERIOD/2;
clk <= '1';
wait for (C_CLK_PERIOD - C_CLK_PERIOD/2);
end process clk_gen;


data_delay(0) <= data;

process(clk)
begin
if clk'event and clk='1' then
for i in 1 to 7 loop
data_delay(i) <= data_delay(i-1);
end loop;
end if;
end process;

dout <= data_delay(7);



-- process(clk,data)
-- begin
-- data_delay(0) <= data;
--
-- if clk'event and clk='1' then
-- for i in 1 to 7 loop
-- data_delay(i) <= data_delay(i-1);
-- end loop;
-- end if;
-- end process;

end behav;

---------- Code ends ----------

I have run vsim with and without the -novopt option as well. and also
tried vcom with -O0 option too.

Thanks
Hemang

 

[Mike Treseler]

I have an small test case below.. This code when simulated with
modelsim v6.4b or d (haven't tried other simulators) give me U on all
the data_delay array elements and also on the dout port. If I move the
data_delay(0) assignment to be within the same process (as shown in
the commented code in the architecture), it starts to work..

That's right.
Except for a tri-state node,
a signal can only be driven by one process.

Otherwise I am shorting two outputs together.

-- Mike Treseler

 

[Hemang]

That's right.
Except for a tri-state node,
a signal can only be driven by one process.

Otherwise I am shorting two outputs together.

    -- Mike Treseler

Thanks Mike.. I am thinking that this is a little too much of a
constrain on interpreting use model of "signals" which are aggregates
of "bits" and "vectors"..

 

[Mike Treseler]

Thanks Mike.. I am thinking that this is a little too much of a
constrain on interpreting use model of "signals" which are aggregates
of "bits" and "vectors"..

Signals, variables and constants are vhdl "objects"
-- containers for values.
Bits and vectors can be of any object.

But I think we agree that signals are unnecessarily
complicated for logic description.
That's why I use variables and single process entities.

-- Mike Treseler

 

[HT-Lab]

Hi,

I have an small test case below.. This code when simulated with
modelsim v6.4b or d (haven't tried other simulators) give me U on all
the data_delay array elements and also on the dout port. If I move the
data_delay(0) assignment to be within the same process (as shown in
the commented code in the architecture), it starts to work..

I was wondering if VHDL LRM stipulates ALL elements of an array to be
assigned within the same "scope", or is this a bug in modelsim?

It is called the longest static prefix, have a look at this question:

http://www.ht-lab.com/question.jpg

The answer is not A.......

Hans
www.ht-lab.com

 

[Hemang]

It is called the longest static prefix, have a look at this question:

http://www.ht-lab.com/question.jpg

The answer is not A.......

Hanswww.ht-lab.com

That is an interesting jpg.. My answer would have been (B), but when I
see my code's results, I expect modelsim to give "UUUUUUUU" as the
answer to your question's code, which is what bothers me..