V
Valentin Tihhomirov
I read (ashenden) that "The operations produce values of the base type
rather than the sub-type. However, the assignment operation will not
assign a value to a variable of a subtype if the value does not meet the
constraint".
I do not understand when this check is performed. One one hand, VHDL
must do this statically, to stay the statically typed lang. On the other
hand, dynamically, because evaluation occurs in simulation and you
cannot check the result before it is produced. I see no way you can
check the range before simulation starts but after it finishes.
rather than the sub-type. However, the assignment operation will not
assign a value to a variable of a subtype if the value does not meet the
constraint".
I do not understand when this check is performed. One one hand, VHDL
must do this statically, to stay the statically typed lang. On the other
hand, dynamically, because evaluation occurs in simulation and you
cannot check the result before it is produced. I see no way you can
check the range before simulation starts but after it finishes.