Bad synchronous description, how to fix it??

[tarzandavid]

hi all,

I met a problem when synthesizing the following code in Xilinx ISE9.2i, saying
" Signal pmu_ready cannot be synthesized ,bad synchronous description ",
I 've compiled and simulated it in ModelSim already,with its function run well, but I fail to figure out what cause the synthesize problem, could anybody give me some advices? Many many thanks!

-----------------------------------------------------------------------------
signal pmu_ready:std_logic;

signal bmu_ready:std_logic; ----- come from another process

signal traceback_ready:std_logic; ----- come from another process

process

begin
if rst='1' then
pmu_ready<='0';
else

if rising_edge(bmu_ready) then
c_pm0:=0;
c_pm1:=0;
c_pm2:=0;
c_pm3:=0;

TB(0)<=(others=>'0');
TB(1)<=(others=>'0');
TB(2)<=(others=>'0');
TB(3)<=(others=>'0');

for i in 0 to 19 loop
........... ---- useless sentences
end loop;

pmu_ready<='1';

end if;

if rising_edge(clk) then
if pmu_ready = '1' then
pmu_ready <='0';
end if;
end if;

if rising_edge(traceback_finish) then
pmu_ready <='0';
end if;
end if;

end process;
-----------------------------------------------------------------------

 

[jeppe]

Well - In generel should a process ONLY contain ONE rising_edge or ONE falling_edge statement.

I succed in having both a falling and rising edge block
but only because the two blocks was working at different signals.

Try to make a drawing of the circuit you expect as a result of your code - I quess your will having big problems doing this and the same is true for the tools.

Best regards
Jeppe

PS! VHDL was first intended as a simulation tool - but even if your allowed to simulate dosn't mean that the code can be synthezised.