Basic VHDL question regarding pins

[googlinggoogler]

Hiya,

Ive just obtained a FPGA spartan 3 board off of ebay for real cheap and
am currently teaching myself VHDL, so far the language seems pretty
nice in terms on syntax, and i dont see any problems with it. However
there is one thing that I havent managed to grasp the concept of,
something so simple that you'll probably sit there giggling to
yourselves. I havent been able to find a definative answer in the
couple of books i scan read (yea yea yea, so i should read them
properly, and I will when i come to actually start work...)

anyway heres my question, in the below code (found on this group), they
define A and B - I would like to know that if theses are ports? not
pins, how would I just access an individual pin? or would I just review
the bits at the port kinda like A = 10101111 (if you see that i mean,
similar to in BASIC), Ive seen things like clk defined in the entity
section,

so my question I suppose is, is there a config file where all this is
defined? how do you know what is what?

cheers

David

<--code-->

library ieee;
use ieee.std_logic_1164.all;

entity InverterConnect is port(
A : in std_logic;
B : out std_logic);
end InverterConnect;

architecture InverterLogic of InverterConnect is
begin
B <= not A;
end;

</--code--/>

 

[Eric Smith]

anyway heres my question, in the below code (found on this group), they
define A and B - I would like to know that if theses are ports? not
pins, how would I just access an individual pin?

You can attach the ports to FPGA pins using attributes or a user constraint
file (UCF). There's a constraint editor in the software that makes this
easy.

or would I just review
the bits at the port kinda like A = 10101111 (if you see that i mean,
similar to in BASIC),

The ports in your example are only one bit each. If you want to deal
with multi-bit data, use std_logic_vector.

Best regards,
Eric