Bit confused by Quartus

[pirx]

Hello All:ciao:

I'm trying to develop sorting network for FPGA using Quartus(it's small university project)

So I defined entity comparator using it I've created Network4 and Network8 entities that sort 4 and 8 numbers.

So far so good. In main project file I have array of 8bit logic vectors from where I'd take data to my networks. (My tutor says it's ok for now to save the data in memory so I could concentrate on presenting the results)

When I compile my project Quartus says that it uses 0 logic cells:shock: and when I run the simulation it instantly gives correct answers. While the RTL viewer is showing correct layout and connections for my networks.

So my answer is would this be working on real Altera chip?

My code looks like that:

begin
data(0) <= "00110111";
...

n1: entity work.network4 port map (data(0), data(1), data(2), data(3), s1, s2, s3, s4);--first four are the inputs, then 4 outputs

Thanks for the help

 

[joris]

Uhm could it be that you are synthesizing the testbench instead of the network4/network8 -- if synthesizing the testbench, it could conclude there is only "dead code" in it (having no inputs/outputs)

 

[pirx]

Uhm could it be that you are synthesizing the testbench instead of the network4/network8 -- if synthesizing the testbench, it could conclude there is only "dead code" in it (having no inputs/outputs)

I got it thanks. That was dead code. Now I need to test it on real hardware