Hello,
I am writing a BPSK demodulator using VHDL for a Xilinx Vertex2 Pro
FPGA. I will be getting IQ data on which I'll do the demodulation.
However, the IQ data has varying phase and frequency offsets which need
to be corrected before hard decision decoding can be carried out.
Has anyone implemented frequency and phase offset removal using
VHDL/fixed point algorithms? How can I approach this. Is there
somewhere I can find code for this?
Is it truly BPSK, i.e. two possible phases 180 degrees apart? If so,
then you can easily spot a phase *transition* by detecting zero-
crossings of both I and Q at roughly the same time. The much
slower phase changes caused by carrier frequency errors will
give rise to zero-crossings of only one of I,Q; and it will
always be the smaller-amplitude component that will change
sign, while the larger-amplitude component stays roughly
constant. A true BPSK transition will have a zero-crossing
(polarity reversal) of the component with *larger* amplitude.
Once you have the phase transitions, you don't really need to
compensate for frequency errors or phase offsets. And I
imagine you will be able to put the data stream back together
from the transitions without too much trouble.
However, once you can tell the difference between phase
drift and phase transitions, it should be easy enough to
extract the phase drift and use it as feedback to the
demodulator. You may wish to Google for "Costas loop"
and "carrier tracking loop" in this context.
To get further I would want to see more detail of the
modulation scheme and data encoding in your system,
as well as details of the carrier, sampling and symbol rates.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
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