building an adder tree for a pipelined fixed point dot product

[wallge]

greetings, I am trying to write a generic fixed point dot product using

generate statements add blocks, register blocks and mul blocks.
I am having trouble figuring out how to do this
there seems to be no ability in vhdl to use variables when doing a for
generate statement.
here's what im trying to do
x = mul block
+ = add block
r = a register

x1 ~ x11 X vector elements
y1 ~ y11 Y vector elements
suppose we want to dot two 11 X 1 vectors together
we could think of this in hardware as a tree of connected multiply then
add blocks

x1 y1 x2 y2 x3 y3 x4 y4 x5 y5 x6 y6 x7 y7 x8 y8 x9 y9 x10 y10
x11 y11
x x x x x x x x
x x x = 11 x's
+ + + +
+ r = 5 +'s, 1 r
+ +
+ = 3 +'s
+
+ = 2 +'s
+
= 1 +

now clearly there has to be a way at each layer in the adder tree to
determine
if we need a register to hold that extra value
if the next layer has an odd number of inputs that register can then be
used as an input to a 2 input adder block
if the next layer has an even number of inputs we have to add an a
register at that level and
send it down to the next level on the next clock value.

what is the best way to handle this within the context of nested for
generate
and if generate statements?