Sandy wrote:
[]
Thats fine,
but my Question is :
The program does not give BUS ERROR on Intel platform (inspite of un-aligned
memory access), But it exits normally with printing some garbage value.
Why does it happen. Is there something different in the memory access
architecture of SPARC and Intel x86
Your question is answered here:
http://msdn.microsoft.com/library/d...l/vcconwindowsdataalignmentonipfx86x86-64.asp
<quote>
In Windows, an application program that generates an alignment fault
will raise an exception, EXCEPTION_DATATYPE_MISALIGNMENT. On the
Itanium, by default, the operating system (OS) will make this exception
visible to the application, and a termination handler might be useful
in these cases. If you do not set up a handler, then your program will
hang or crash. In Listing 3 we provide an example that shows how to
catch the EXCEPTION_DATATYPE_MISALIGNMENT exception.
....
The application can change the behavior of the alignment fault from the
default, to one where the alignment fault is fixed up. This is done
with the Win API call, SetErrorMode, with the argument field
SEM_NOALIGNMENTFAULTEXCEPT set. This allows the OS to handle the
alignment fault, but at considerable performance cost. Two things to
note: 1) this is on a per process basis, so each process should set
this before the first alignment fault, and 2)
SEM_NOALIGNMENTFAULTEXCEPT is sticky, that is, if this bit is ever set
in an application through SetErrorMode then it can never be reset for
the duration of the application (inadvertently or otherwise).
On the x86 architecture, the operating system does not make the
alignment fault visible to the application. On these two platforms,
you'll also suffer performance degradation on the alignment fault, but
it will be significantly less severe than on the Itanium, as the
hardware will make the multiple accesses of memory to retrieve the
unaligned data.
On the x86-64 architecture, the alignment exceptions are disabled by
default, and the fix-ups are done by the hardware. The application can
enable alignment exceptions by setting a couple of register bits, in
which case the exceptions will be raised unless the user has the
operating system mask the exceptions with SEM_NOALIGNMENTFAULTEXCEPT.
(For details, see the AMD x86-64 Architecture Programmer's Manual
Volume 2: System Programming.)
</quote>