M
majmoat_ensan
hi all,
really i want a help in these 2 problems :
1)
I want a structural VHDL code of 1 to 16 Demultiplexers. with an
active low Enable signal using 1 to 2 Demultiplexer. [ use Generate
statement]
__________________________________________________ ____________
2)
Also I need a structure and behavior VHDL code of 5-bits binary
counter with a synchronous load signal to preset the counter to a
specific initial state. the output of the counter ( Q0 to Q4) are
connected to a binary decoder that shows the state of the counter.
really i want a help in these 2 problems :
1)
I want a structural VHDL code of 1 to 16 Demultiplexers. with an
active low Enable signal using 1 to 2 Demultiplexer. [ use Generate
statement]
__________________________________________________ ____________
2)
Also I need a structure and behavior VHDL code of 5-bits binary
counter with a synchronous load signal to preset the counter to a
specific initial state. the output of the counter ( Q0 to Q4) are
connected to a binary decoder that shows the state of the counter.