Cannot compile with subprogramm

[tgschwind]

I got a piece of VHDL which I cannot compile it with ModelSim 6.0 SE,
when calling vcom I get the error: "Cannot call subprogram "to_analog"
before it is elaborated."

As I have understand it is because the the function is used after it
was declaread, but before it was actually writen in the package. See
code:

package xyz_pkg is
....
subtype analog is std_logic_vector(PW-1 downto 0);
....
function to_analog (constant value : real) return analog;
function to_analog (constant value : integer) return analog;
....
constant VDDP : analog := to_analog(3.3);
constant VTH : analog := to_analog(1.3);
constant VDDH : analog := to_analog(5.0);
constant VSS : analog := to_analog(0.0);
constant GND : analog := to_analog(0.0);

end xyz_pkg;

package body xyz_pkg is
....
-- purpose: convert real to analog
function to_analog (constant value : real) return analog is
begin
return analog(to_signed(integer(value*(2.0**(PW-IP))), PW));
end to_analog;

-- purpose: convert integer to analog
function to_analog ( constant value : integer) return analog is
begin
return analog(to_signed(value, PW));
end to_analog;
.....
end xyz_pkg;

If there an option in ModelSim to allow such a programming, or do I
have to change it. It works under NCSim.

 

[john Doef]

(e-mail address removed) a écrit :

I got a piece of VHDL which I cannot compile it with ModelSim 6.0 SE,
when calling vcom I get the error: "Cannot call subprogram "to_analog"
before it is elaborated."

As I have understand it is because the the function is used after it
was declaread, but before it was actually writen in the package. See
code: [...]
Correct.

If there an option in ModelSim to allow such a programming, or do I
have to change it. It works under NCSim.

No, you'd better to change it. After all, here ModelSim closely follow
the LRM.
The best option is certainly to create a package for analog type and
the subprograms,
and another package for your constants.

JD.

 

[Ralf Hildebrandt]

I got a piece of VHDL which I cannot compile it with ModelSim 6.0 SE,
when calling vcom I get the error: "Cannot call subprogram "to_analog"
before it is elaborated." ....
If there an option in ModelSim to allow such a programming, or do I
have to change it. It works under NCSim.

I don't know ModelSim, but for NCSim there is a (silly) option, to
compile packages or to compile them not. (NCSim just ignores packages,
if this switch is turned off, but gives no warning. Everything seems to
be compiled well, but isn't.) Maybe there is a similar switch in ModelSim.

Ralf

 

[Mike Treseler]

I got a piece of VHDL which I cannot compile it with ModelSim 6.0 SE,
when calling vcom I get the error: "Cannot call subprogram "to_analog"
before it is elaborated."

So, defer the constant declarations as shown below.
This compiles fine with vcom.

-- Mike Treseler
---------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package xyz_pkg is
constant PW : natural := 18;
constant IP : natural := 2;
subtype analog is std_logic_vector(PW-1 downto 0);
-- deferred constant declarations here make
-- these visible after definition in body below
constant VDDP : analog;
constant VTH : analog;
constant VDDH : analog;
constant VSS : analog;
constant GND : analog;
function to_analog (constant value : real) return analog;
function to_analog (constant value : integer) return analog;
end xyz_pkg;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package body xyz_pkg is
-- purpose: convert real to analog
function to_analog (constant value : real) return analog is
begin
return analog(to_signed(integer(value*(2.0**(PW-IP))), PW));
end to_analog;
-- purpose: convert integer to analog
function to_analog (constant value : integer) return analog is
begin
return analog(to_signed(value, PW));
end to_analog;
-- deferred constants definitions must follow function definition
constant VDDP : analog := to_analog(3.3);
constant VTH : analog := to_analog(1.3);
constant VDDH : analog := to_analog(5.0);
constant VSS : analog := to_analog(0.0);
constant GND : analog := to_analog(0.0);
end xyz_pkg;

 

[tgschwind]

Thanks, that resolved the problem, works now with Modelsim and NC.