clocked signals

[john]

Hello,

I am having problem Switching the address bus of the sram with
the data bus.
I tried different things but nothing worked. States "A1" and "A2"
working perfectly right and I am getting the correct data out of the
ram .
Data retireved from the state "A2" supposed to become new address in
state
"A3" and in State "A4", I should get the final data...
Now, according to data stored in the RAM ( as mentioned in the table),
at "0000..00",
I should get"00000000000101" and then by making it address, I should
get "00000000010001".
But instead of getting this value I am getting garbage or other written
values. I am using
atmel prochip software so I do not have good simulator, so I am doing
alltesting on my hardware....
Please advice!
Thanks
john


Table
Addresses Data

00000000000000 00000000000101

00000000000101 00000000010001

--------------------------------------------------

Architecture DPR_ARCH of Read is
Begin
Output_Enable <= '0';
CE0 <= '0';
CE1 <= '1';
Read_write <= '1';
Latch <= sel_14bit_mux ;

Address_bus( 13 downto 0)<= TEMP When sel_14bit_mux='0'
Else
"00000000000000";

Address_bus( 18 downto 14)<= "00000";
Data_out_bus(13 downto 0)<= TEMP;



Process ( State_A,input_signal )

Begin

Case State_A is


When A1 =>
--First Address get Valid --

incr_B <='0';
LBL <='1';
UBL <='1';
sel_14bit_mux <='1';

nextstate_A <= A2;

When A2 =>
--Data is valid on the Bus --
incr_B <='0';
LBL <='0';
UBL <='0';
sel_14bit_mux <='1';
TEMP <= Data_Bus;

nextstate_A <= A3;

When A3 =>
--Data becomes Address --

incr_B <='1';
LBL <='1';
UBL <='1';
sel_14bit_mux <='0';

nextstate_A <= A4;

When A4 =>
--Data is out --

incr_B <='1';
LBL <='0';
UBL <='0';
sel_14bit_mux <='0';
TEMP <=Data_Bus;

nextstate_A <= A1;


When others =>
nextstate_A <= A0;
End Case;
End Process;



Process ( DPR_CLK)

Begin


If(DPR_CLK 'event And DPR_CLK ='1') Then


State <= nextstate;
State_A <= nextstate_A;

End If;

End Process;

 

[Mike Treseler]

But instead of getting this value I am getting garbage or other written
values. I am using
atmel prochip software so I do not have good simulator, so I am doing
alltesting on my hardware....

This sort of problem is best solved by simulation.
Consider the free version of sonata.

-- Mike Treseler

 

[zingafriend]

First of all the way the FSM is written is not correct.
You have to include the databus signal also in the sensitivity list
else you'll end up with latches.
You have not assigned to temp in other states which will also lead to
latches.
There is no initialization for your code, resulting in no initial state
in which to start, your default state A0 dosent exist.
After, all the above corrections, the better way would be to assign to
address and data explicitly in every state. then it should certainly
work.

 

[zingafriend]

Your FSM coding in not correct as
You have not included the databus in the sensitivity list.
Temp is not assigned in other states resulting in latches.
You dont have an initial state to start, your default state A0 dosent
exist.
With above corrections, it would be better if you made assignments to
address and data bus explicitly in each of the states.

-Neo