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- Jul 10, 2007
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Hello All..
I have made one code for 24 mhz to 434Khz (Frequency divider)..
Actually in my project, i have 24 Mhz clock freqency and i want to convert it into 434 Khz...
My code is..
Library IEEE;
Use IEEE.std_logic_1164.all;
Entity FA is
port(clk :in bit;
clkout : out bit);
End Entity FA;
Architecture FA_calc of FA is
begin
process(clk)
variable cnt : integer range 0 to 28;
begin
if(clk'event and clk='1') then
if(cnt = 28 ) then
clkout<='1';
else
cnt := cnt+1;
clkout<='0';
end if;
end if;
end process;
End Architecture FA_calc;
Is it correct or not ??
ie cnt should be 28 (Twenty-eight) or 56 that i dont know..
Thanks a lot..
I have made one code for 24 mhz to 434Khz (Frequency divider)..
Actually in my project, i have 24 Mhz clock freqency and i want to convert it into 434 Khz...
My code is..
Library IEEE;
Use IEEE.std_logic_1164.all;
Entity FA is
port(clk :in bit;
clkout : out bit);
End Entity FA;
Architecture FA_calc of FA is
begin
process(clk)
variable cnt : integer range 0 to 28;
begin
if(clk'event and clk='1') then
if(cnt = 28 ) then
clkout<='1';
else
cnt := cnt+1;
clkout<='0';
end if;
end if;
end process;
End Architecture FA_calc;
Is it correct or not ??
ie cnt should be 28 (Twenty-eight) or 56 that i dont know..
Thanks a lot..
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