R
rahul.bajait30
can anybody tell me whats wrong in the following code ::
library ieee,std;
use std.textio.all;
use ieee.std_logic_textio.all;
entity len is
end len;
architecture length of len is
signal final : integer := 0;
begin
process
file infile : text is in "E:\shweta\extra\RCS card\examples
\data.dat";
file outfile :text is out "E:\shweta\extra\RCS card
\examples\out.dat";
variable inlin : line;
variable outlin : line;
variable length : integer := 0;
begin
while(not(endfile(infile))) loop
readline(infile,inlin);
wait for 100 ns;
length := length + inlin'length;
deallocate(inlin);
end loop;
final <= length;
end process;
end length;
library ieee,std;
use std.textio.all;
use ieee.std_logic_textio.all;
entity len is
end len;
architecture length of len is
signal final : integer := 0;
begin
process
file infile : text is in "E:\shweta\extra\RCS card\examples
\data.dat";
file outfile :text is out "E:\shweta\extra\RCS card
\examples\out.dat";
variable inlin : line;
variable outlin : line;
variable length : integer := 0;
begin
while(not(endfile(infile))) loop
readline(infile,inlin);
wait for 100 ns;
length := length + inlin'length;
deallocate(inlin);
end loop;
final <= length;
end process;
end length;