Code not working for Quartus 2

[shah_satish2002]

Hi..I have made my VHDL code in Altera model Sim.Its working in Altera model sim but its showing error in Quartus 2..Can any boday help me whats error ??

1st file :-

library IEEE;
use IEEE.std_logic_1164.all;

package mem is
constant width : INTEGER := 4;
constant mem_raw : INTEGER := 7;

type word1 is Array(0 to mem_raw) of std_logic_vector(width-1 downto 0);
type word2 is array(0 to (mem_raw-1)*2) of std_logic;
--type Type_word is std_logic_vector(width-1 downto 0) of word;

end mem;

2nd file :-

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.mem.all;

entity FA_calc is
port( clk : std_logic;
MTmux : in std_logic_vector(width-2 downto 0);
MTdat : in std_logic_vector(width-2 downto 0);
MTout : out word2;
MTout_analyzer : out std_logic_vector(width-2 downto 0);
load : in std_logic
);
end FA_calc;

architecture behav of FA_calc is
signal sig_mem, sig_out : word1;
signal counter : std_logic_vector(12 downto 0) := "0000000000000";
signal clkenable : std_logic;
begin

clkdiv : process(clk)
begin
if clk = '1' and clk'event and clkenable = '1' then
counter <= counter + 1;
end if;
end process;

----decoder and data transfer code----
trans : process(MTmux, counter)
begin
clkenable <= '1';
if counter = "1101001000000" then
case MTmux is
when "000" =>
sig_mem(0)(width-1 downto 1) <= MTdat;
when "001" =>
sig_mem(1)(width-1 downto 1) <= MTdat;
when "010" =>
sig_mem(2)(width-1 downto 1) <= MTdat;
when "011" =>
sig_mem(3)(width-1 downto 1) <= MTdat;
when "100" =>
sig_mem(4)(width-1 downto 1) <= MTdat;
when "101" =>
sig_mem(5)(width-1 downto 1) <= MTdat;
when "110" =>
sig_mem(6)(width-1 downto 1) <= MTdat;
when others =>
NULL;
end case;
counter <= "0000000000000";
clkenable <= '0';
end if;
end process trans;

---load data to output---
ld : process(load)
begin
if load'event then ---- depend on the switch
sig_mem(0)(0) <= '0';
sig_mem(1)(0) <= load;

for i in 0 to 5 loop

case sig_mem(i+1) is
when "0000" =>
sig_out(i+1)(width-2 downto 0) <= "000";
when "0100" =>
sig_out(i+1)(width-2 downto 0) <= "000";
when "1100" =>
sig_out(i+1)(width-2 downto 0) <= "001";
when "1110" =>
sig_out(i+1)(width-2 downto 0) <= "001";
when "0110" =>
sig_out(i+1)(width-2 downto 0) <= "011";
when "0010" =>
sig_out(i+1)(width-2 downto 0) <= "011";
when "1010" =>
sig_out(i+1)(width-2 downto 0) <= "010";
when "1011" =>
sig_out(i+1)(width-2 downto 0) <= "010";
when "0011" =>
sig_out(i+1)(width-2 downto 0) <= "110";
when "0111" =>
sig_out(i+1)(width-2 downto 0) <= "110";
when "1111" =>
sig_out(i+1)(width-2 downto 0) <= "111";
when "1101" =>
sig_out(i+1)(width-2 downto 0) <= "111";
when "0101" =>
sig_out(i+1)(width-2 downto 0) <= "101";
when "0001" =>
sig_out(i+1)(width-2 downto 0) <= "101";
when "1001" =>
sig_out(i+1)(width-2 downto 0) <= "100";
when "1000" =>
sig_out(i+1)(width-2 downto 0) <= "100";
when others =>
NULL;
end case;

sig_mem(i+2)(0) <= sig_out(i+1)(width-2);

end loop;

end if;
end process ld;

---data out---
MTout_analyzer <= sig_mem(0)(width-1 downto 1);
MTout(0) <= sig_out(1)(width-3);
MTout(1) <= sig_out(1)(width-2);
MTout(2) <= sig_out(2)(width-3);
MTout(3) <= sig_out(2)(width-2);
MTout(4) <= sig_out(3)(width-3);
MTout(5) <= sig_out(3)(width-2);
MTout(6) <= sig_out(4)(width-3);
MTout(7) <= sig_out(4)(width-2);
MTout(8 ) <= sig_out(5)(width-3);
MTout(9) <= sig_out(5)(width-2);
MTout(10) <= sig_out(6)(width-3);
MTout(11) <= sig_out(6)(width-2);
MTout(12) <= sig_out(6)(width-1);

end behav;


Error (10633): VHDL Case Statement or If Statement error at FA_calc.vhd(62): can't synthesize condition that contains an isolated 'EVENT predefined attribute.

Error: Can't elaborate top-level user hierarchy

Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 10 warnings
Info: Allocated 143 megabytes of memory during processing
Error: Processing ended: Tue Jul 31 09:35:43 2007
Error: Elapsed time: 00:00:02

Error: Quartus II Full Compilation was unsuccessful. 2 errors, 10 warnings

Please help me out..

Thanks a lot.