code synthesis problem in file read operation

[sudhakar_bansal]

hi
i m facing a strange problem while synthesizing the code written in VHDL
my code goes on like:

library ieee,std;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use work.components.dwt_1d_quant;

entity dwt_2d is
port ( clk : in std_logic;
rst : in std_logic;
temp_1 : inout std_logic_vector(7 downto 0);
hpc : out std_logic_vector(8 downto 0);
lpc : out std_logic_vector(7 downto 0));
end dwt_2d;

architecture dwt_2d of dwt_2d is
file pix_file:text open read_mode is "data.txt";
begin
dwt_1d_quant_1:dwt_1d_quant
port map(input=>temp_1,clk=>clk,rst=>rst,hpc=>hpc,lpc=>lpc);
process(clk,rst)
variable pix_line:line;
variable pix_val:bit_vector(7 downto 0);
variable read_ok:boolean;
begin
if (rst='1') then temp_1<=(others=>'0');
elsif (clk='1' and clk'event) then
if (not endfile(pix_file)) then
read(pix_line,pix_val,read_ok);
temp_1<=to_stdlogicvector(pix_val);
if (not(read_ok)) then
readline(pix_file,pix_line);
read(pix_line,pix_val,read_ok);
temp_1<=to_stdlogicvector(pix_val);
end if;
end if;
end if;
end process;
end dwt_2d;


First problem is that i am unable to use only one read operation under if-else condition. I have tried to use pix_line'length but that is also unsynthesizable.

Second is that when i try to synthesize the code it gives the error:
ERROR:Xst:1922 - "<file_name.vhd>" line 28: Line <pix_line> must have a constant value.

Please help
Sudhakar Bansal