F
Frank Buss
I have a generic entity with a signals like this:
writeAddress: out unsigned(ADDRESS_WIDTH-1 downto 0);
dstStart: in unsigned(ADDRESS_WIDTH-1 downto 0);
dstPitch: in unsigned(15 downto 0);
Then I have a procedure:
procedure setPixel(x: unsigned(15 downto 0); y: unsigned(15 downto 0)) is
begin
writeAddress <= dstStart + dstPitch * y + x;
writeEnable <= '1';
data <= color;
end;
Xilinx ISE compiles it, but generates a warning:
Width mismatch. <writeAddress> has a width of 14 bits but assigned
expression is 32-bit wide
IIRC in Quartus this would be an error. So to avoid the warning, I have
written this function:
function adjustLength(value: unsigned; length: natural) return unsigned is
variable result: unsigned(length-1 downto 0);
begin
if value'length > length then
result := value(length-1 downto 0);
else
result := to_unsigned(0, length - value'length) & value;
end if;
return result;
end;
Now I can write it like this:
writeAddress <= adjustLength(
dstStart + dstPitch * y + x,
writeAddress'length);
and there is no warning anymore, but I wonder if this is good VHDL coding
style, or if there is already library function which does this. I want to
avoid using integer variables with ranges, because then I don't need too
many conversions for other operations for the block RAM interface and
parameter passing from external devices, which are all unsigned vectors.
I'm using this use-statements:
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
writeAddress: out unsigned(ADDRESS_WIDTH-1 downto 0);
dstStart: in unsigned(ADDRESS_WIDTH-1 downto 0);
dstPitch: in unsigned(15 downto 0);
Then I have a procedure:
procedure setPixel(x: unsigned(15 downto 0); y: unsigned(15 downto 0)) is
begin
writeAddress <= dstStart + dstPitch * y + x;
writeEnable <= '1';
data <= color;
end;
Xilinx ISE compiles it, but generates a warning:
Width mismatch. <writeAddress> has a width of 14 bits but assigned
expression is 32-bit wide
IIRC in Quartus this would be an error. So to avoid the warning, I have
written this function:
function adjustLength(value: unsigned; length: natural) return unsigned is
variable result: unsigned(length-1 downto 0);
begin
if value'length > length then
result := value(length-1 downto 0);
else
result := to_unsigned(0, length - value'length) & value;
end if;
return result;
end;
Now I can write it like this:
writeAddress <= adjustLength(
dstStart + dstPitch * y + x,
writeAddress'length);
and there is no warning anymore, but I wonder if this is good VHDL coding
style, or if there is already library function which does this. I want to
avoid using integer variables with ranges, because then I don't need too
many conversions for other operations for the block RAM interface and
parameter passing from external devices, which are all unsigned vectors.
I'm using this use-statements:
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;