Hi ... I'm hoping someone could comment on my code.
It compiles fine in model sim but I just don't think it'll work
Anywhos ... here it is:
------------------------------------------------------------------
ibrary IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.Numeric_STD.all;
entity statemachine is
port(
clock : in std_logic;
reset : in std_logic;
in_pin : in std_logic;
out_pin: in std_logic;
empty : out std_logic;
full : out std_logic;
err : out std_logic;
number : out std_logic_vector (7 downto 0)
);
end;
architecture struct of statemachine is
type state is (S_ERROR, S_FULL, S_EMPTY, S_ADD, S_SUB, S_NORMAL); -- 11 states
signal next_state,current_state : state;
begin
--------------------------------
-- RESET PROCEDURE
--------------------------------
zero : process(clock)
begin
if (reset = '1') then
current_state <= S_EMPTY; --go to empty state
number <= "00000000"; --reset counter to zerp
err <= '0'; --error value = 0
full <= '0'; --full = 0
empty <= '1'; --empty = 1 as full reset
elsif rising_edge(clock) then
current_state <= next_state; --on each clock cycle, move to next state
else null;
end if;
end process zero;
------------------------------
-- STATE MACHINE
------------------------------
states : process(current_state, in_pin, out_pin)
variable v_state : state;
variable v_err, v_full, v_empty : std_logic;
variable v_number : std_logic_vector(7 downto 0);
begin
case v_state is
when S_ERROR =>
v_err := '1';
v_state := S_ERROR;
when S_FULL =>
if (in_pin = '1') then
v_state := S_ERROR;
elsif (out_pin = '1') then
v_number := v_number - 1;
v_state := S_NORMAL;
else null;
end if;
when S_EMPTY =>
if (out_pin = '1') then
v_state := S_ERROR;
elsif (in_pin = '1') then
v_number := v_number + 1;
v_state := S_NORMAL;
else null;
end if;
when S_ADD =>
if (v_number = "11111110") then
v_number := "11111111";
v_state := S_FULL;
else
v_number := v_number + 1;
v_state := S_NORMAL;
end if;
when S_SUB =>
if (v_number = "00000001") then
v_number := "00000000";
v_state := S_EMPTY;
else
v_number := v_number - 1;
v_state := S_NORMAL;
end if;
when S_NORMAL =>
v_full := '0';
v_empty := '0';
if rising_edge(in_pin) then
v_state := S_ADD;
elsif rising_edge(out_pin) then
v_state := S_SUB;
else null;
end if;
when others => null;
end case;
next_state <= v_state;
err <= v_err;
full <= v_full;
empty <= v_empty;
number <= v_number;
end process;
end struct;
-------------------------------------------------------------------
Its been a while since I played with VHDL. I can't remember how to assign the initial state without assigning 1 to the reset pin.
Anything constructive is welcomed =)
It compiles fine in model sim but I just don't think it'll work
Anywhos ... here it is:
------------------------------------------------------------------
ibrary IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.Numeric_STD.all;
entity statemachine is
port(
clock : in std_logic;
reset : in std_logic;
in_pin : in std_logic;
out_pin: in std_logic;
empty : out std_logic;
full : out std_logic;
err : out std_logic;
number : out std_logic_vector (7 downto 0)
);
end;
architecture struct of statemachine is
type state is (S_ERROR, S_FULL, S_EMPTY, S_ADD, S_SUB, S_NORMAL); -- 11 states
signal next_state,current_state : state;
begin
--------------------------------
-- RESET PROCEDURE
--------------------------------
zero : process(clock)
begin
if (reset = '1') then
current_state <= S_EMPTY; --go to empty state
number <= "00000000"; --reset counter to zerp
err <= '0'; --error value = 0
full <= '0'; --full = 0
empty <= '1'; --empty = 1 as full reset
elsif rising_edge(clock) then
current_state <= next_state; --on each clock cycle, move to next state
else null;
end if;
end process zero;
------------------------------
-- STATE MACHINE
------------------------------
states : process(current_state, in_pin, out_pin)
variable v_state : state;
variable v_err, v_full, v_empty : std_logic;
variable v_number : std_logic_vector(7 downto 0);
begin
case v_state is
when S_ERROR =>
v_err := '1';
v_state := S_ERROR;
when S_FULL =>
if (in_pin = '1') then
v_state := S_ERROR;
elsif (out_pin = '1') then
v_number := v_number - 1;
v_state := S_NORMAL;
else null;
end if;
when S_EMPTY =>
if (out_pin = '1') then
v_state := S_ERROR;
elsif (in_pin = '1') then
v_number := v_number + 1;
v_state := S_NORMAL;
else null;
end if;
when S_ADD =>
if (v_number = "11111110") then
v_number := "11111111";
v_state := S_FULL;
else
v_number := v_number + 1;
v_state := S_NORMAL;
end if;
when S_SUB =>
if (v_number = "00000001") then
v_number := "00000000";
v_state := S_EMPTY;
else
v_number := v_number - 1;
v_state := S_NORMAL;
end if;
when S_NORMAL =>
v_full := '0';
v_empty := '0';
if rising_edge(in_pin) then
v_state := S_ADD;
elsif rising_edge(out_pin) then
v_state := S_SUB;
else null;
end if;
when others => null;
end case;
next_state <= v_state;
err <= v_err;
full <= v_full;
empty <= v_empty;
number <= v_number;
end process;
end struct;
-------------------------------------------------------------------
Its been a while since I played with VHDL. I can't remember how to assign the initial state without assigning 1 to the reset pin.
Anything constructive is welcomed =)