Hello David,
Some observations and looking for your insight regarding the fixed_pkg.
I tried synthesizing a simple fixed point multiplier block, initially
with Precision Synthesis from Mentor (because I am having trouble
synthesizing with the Altera tool).
--Observations:
1)
Precision complains about the aliases on lines 594 and 595 of
fixed_pkg.vhd, but has no complaints about the aliases on lines 588 and
589. I am assuming this is a bug and if so, I can report it a a bug to
Mentor support. For now, I've commented the two lines and hoping that
it does not affect the functionality of my code.
2)
Below is the code for the fixed point multiplier that I synthesized.
The block multiplies (A x B) where:
A : a 9 bit signed integer
B : a 4 bit fraction (i.e the fraction is 0.b1b2b3b3 so four bits
after the decimal)
C : result is 14 bits.
But when I look at the RTL schematic from Precision synthesis, it uses
a 26 bit multiplier.
Is this expected or am I using the package incorrectly?
I would appreciate any insight into this.
Thank you
---- Code for fixed point multiplier
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY work;
USE work.fixed_pkg.all;
ENTITY mytest IS
PORT(
CLK : in std_logic;
A : in std_logic_vector(8 downto 0);
B : in std_logic_vector(3 downto 0);
reset : in std_logic;
C : out std_logic_vector(13 downto 0)
);
END mytest;
--
ARCHITECTURE rtl OF mytest IS
signal ans : sfixed(8 downto -5);
BEGIN
process (clk, reset)
variable aint : sfixed(8 downto -1);
variable bint : sfixed(0 downto -4);
begin
if (reset = '1') then
ans <= (others => '0');
aint := (others => '0');
bint := (others => '0');
elsif (clk = '1' and clk'event) then
aint(8 downto 0) := to_sfixed(A,8,0);
aint(-1) := '0';
bint(-1 downto -4) := to_sfixed(B,-1,-4);
bint(0) := '0';
ans <= aint * bint;
end if;
end process;
C <= to_slv(ans);
END rtl;
