Compile model error

[Tony Benham]

Hi,
I'm compiling a model from Micron Semi written in vhdl and am getting the
following modelsim compile error.
"select choice must be a locally static expression"
The vhdl involved is
WITH C SELECT
C_Int <= K AFTER tCHCQV WHEN C_n,
C AFTER tCHCQV WHEN NOT(C_n),
K AFTER tCHCQV WHEN OTHERS;
where C_Int, C_n are STD_LOGIC.
Unless this is a vhdl-93/87 problem, I am puzzled how can it ever have
worked ?
Is there a simple solution to this ?
TIA
Tony

 

[Jonathan Bromley]

Hi,
I'm compiling a model from Micron Semi written in vhdl and am getting the
following modelsim compile error.
"select choice must be a locally static expression"
The vhdl involved is
WITH C SELECT
C_Int <= K AFTER tCHCQV WHEN C_n,
C AFTER tCHCQV WHEN NOT(C_n),
K AFTER tCHCQV WHEN OTHERS;
where C_Int, C_n are STD_LOGIC.
Unless this is a vhdl-93/87 problem, I am puzzled how can it ever have
worked ?

Me too. Some tools tolerate this kind of thing, or have a switch
that allows the strict VHDL limitation to be relaxed, so perhaps
that's how they got away with it.

Is there a simple solution to this ?

Replace the whole WITH clause by the following process,
which (I think) does the same thing:

process (C, C_n, K) begin
if C = not C_n then
C_Int <= C after tCHCQV;
else
C_Int <= K after tCHCQV;
end if;
end process;

If C and/or K are constants then of course
they shouldn't be in the sensitivity list, but I
assume they are signals.

WITH...SELECT is incredibly ugly anyhow. I completely fail
to understand why anyone tries to use it. (Just my bigoted
personal opinion, of course!)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.