Hallo all.
I use this component
component fjkce
port(CLR,CE, J,K,C:IN BIT; Q: OUT BIT);
end component;
And when i compile Code (Xilinx ISE), become this warning:
WARNING:Xst:2036 - Inserting OBUF on port <q> driven by black box <fjkce>. Possible simulation mismatch.
For example when i use fd, and3, or3... i become this warning not. With PORT declaration is all good. I click on "View Technology Schematic" to see schematic, and there it's all right. But respecting this warning i can't normaly use Wave Form Testbench, because output ist passive....
I use this component
component fjkce
port(CLR,CE, J,K,C:IN BIT; Q: OUT BIT);
end component;
And when i compile Code (Xilinx ISE), become this warning:
WARNING:Xst:2036 - Inserting OBUF on port <q> driven by black box <fjkce>. Possible simulation mismatch.
For example when i use fd, and3, or3... i become this warning not. With PORT declaration is all good. I click on "View Technology Schematic" to see schematic, and there it's all right. But respecting this warning i can't normaly use Wave Form Testbench, because output ist passive....