Components in VHDL

[samehsh]

next code give me the following warning:---------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Point_Doubling is
Port ( X1 : in STD_LOGIC_VECTOR (191 downto 0);
Z1 : in STD_LOGIC_VECTOR (191 downto 0);
X2 : out STD_LOGIC_VECTOR (191 downto 0);
Z2 : out STD_LOGIC_VECTOR (191 downto 0)
);
end Point_Doubling;

architecture Behavioral of Point_Doubling is
component BmultKaratsuba191 is
port( busA : in std_logic_vector(191 downto 0);
busB : in std_logic_vector(191 downto 0);
RbusR : out std_logic_vector(191 downto 0));
end component;

component FF_Square is
port( A : in std_logic_vector(191 downto 0);
RbusR : out std_logic_vector(191 downto 0));
end component;
Signal T :std_logic_vector(191 downto 0);
Signal ZSQR :std_logic_vector(191 downto 0);
Signal TSQR :std_logic_vector(191 downto 0);

begin

SQR1:FF_Square port map(X1(191 downto 0),T(191 downto 0));

SQR2:FF_Square port map(Z1(191 downto 0),ZSQR(191 downto 0));

mul1:BmultKaratsuba191 port map(T(191 downto 0),ZSQR(191 downto 0),Z2(191 downto 0));

SQR3:FF_Square port map(T(191 downto 0),TSQR(191 downto 0));

X2<=TSQR xor ZSQR;

end Behavioral;

Warning

WARNING:Xst:647 - Input <A<191>> is never used.
WARNING:Xst:653 - Signal <square_A<381>> is used but never assigned. Tied to value 0.
WARNING:Xst:646 - Signal <Mult3rd<255:254>> is assigned but never used.
WARNING:Xst:1290 - Hierarchical block <SQR1> is unconnected in block <Point_Doubling>.
WARNING:Xst:1290 - Hierarchical block <SQR2> is unconnected in block <Point_Doubling>.
WARNING:Xst:1290 - Hierarchical block <compAND1> is unconnected in block <mul1>.
WARNING:Xst:1290 - Hierarchical block <compAND2> is unconnected in block <mul1>.
WARNING:Xst:1290 - Hierarchical block <compAND61> is unconnected in block <mul1>..........................................

i check the components of this design but it work in a good mannar....but i don't know why this code give this warnning
-----------------------------------------
also how can i divide my design to some of clock cycles