Concatenation in PROCEDURE call

[Analog_Guy]

I am trying to implement a testbench to generically test n-input
combinatorial functions. My problem lies in trying to make 1 generic
PROCEDURE to handle any combination of n-input functions.

I tried the following, but it did not work:

The procedure call:
test_comb (dut_in_1 & dut_in_2 & dut_in_3, dut_out);

The procedure:
PROCEDURE test_comb ( SIGNAL dut_in : INOUT STD_LOGIC_VECTOR;
SIGNAL dut_out : IN STD_LOGIC) IS
Where:
dut_in_x are the circuit inputs (i.e. testbench outputs for
driving)
dut_out is the circuit ouput (i.e. testbench input for
verification)
dut_in within the PROCEDURE is an unconstrained array

I thought I could use concatenation in a PROCEDURE call. My intention
was to pass the variable number of outputs as as array, and then use
'LENGTH within the PROCEDURE to figure out the width.

ModelSim gives the following warning: "Parameter modes do not conform
for dut_in"?

It appears that I cannot use concatenation with outputs or inouts, but
I don't know how else to tackle the problem?

 

[Paul Uiterlinden]

I am trying to implement a testbench to generically test n-input
combinatorial functions. My problem lies in trying to make 1 generic
PROCEDURE to handle any combination of n-input functions.

I tried the following, but it did not work:

The procedure call:
test_comb (dut_in_1 & dut_in_2 & dut_in_3, dut_out);

The procedure:
PROCEDURE test_comb ( SIGNAL dut_in : INOUT STD_LOGIC_VECTOR;
SIGNAL dut_out : IN STD_LOGIC) IS
Where:
dut_in_x are the circuit inputs (i.e. testbench outputs for
driving)
dut_out is the circuit ouput (i.e. testbench input for
verification)
dut_in within the PROCEDURE is an unconstrained array

I thought I could use concatenation in a PROCEDURE call.

Yes, you can, but not if the formal parameter is a signal.
(By the way: why is dut_in INOUT, in stead of OUT?)

If the formal parameter really needs to be a signal, than you need an
intermediate signal to do the concatenation:

test_comb (dut_in, dut_out);
dut_in <= dut_in_1 & dut_in_2 & dut_in_3;

Where dut_in is a 3 bit wide std_logic_vector signal.

Paul.