concatenation - VHDL

[MariuszK]

Hello,
--N,K constant and N+3=>K and K>3
signal s1: std_logic_vector(N-1 downto 0);
signal s2: std_logic_vector(K-1 downto 0);

For diffrent N i K I have to write diffrent code
s2<= "0" & s1 & "000";
s2<= "00" & s1 & "000";
s2<= "000" & s1 & "000";
s2<= "0000" & s1 & "000";
etc...

Is it possibility write somethink like this??
s2<= "others=>'0' " & s1 & "000";

Best regards
Mariusz

 

[jeppe]

Hi Marius Z

I believe the best way to do the trick will be an integer;
My idea shown below - hope its useful

Jeppe

signal i: integer;

i <= Conv_integer( s1 & "000");
s2 <= conv_std_logic_vector( i, K-1);

 

[MariuszK]

No, but how about this procedural code:

  s2 <= (others => '0');
  s2(N+2 downto 3) <= s1;

Or, if s1 and s2 are of numeric_std.unsigned type:

  s2 <= resize(s1 & "000", s2'length);

Or, if you are a masochist:

  s2 <= (K-1 downto N+3 => '0') & s1 & "000";

Best of all, write a custom function to do what
you want.  Then you can use for-loops and suchlike
inside the function, but simply call it like this:

  s2 <= insert_shifted(s1, 3, K);

Implementation:

  function insert_shifted
    ( new_data     : std_logic_vector
    ; left_shift   : natural
    ; result_width : positive
    ) return std_logic_vector is
    variable result: std_logic_vector(result_width-1 downto 0);
    constant d_width: natural := new_data'length;
  begin
    assert result_width >= d_width + left_shift
      report "output (" & integer'image(result_width)
           & " bits) is too narrow for new_data ("
           & integer'image(d_width)
           & " bits) left-shifted by " & integer'image(left_shift)
      severity error;
    result := (others => '0');
    result(d_width + left_shift - 1 downto left_shift) := new_data;
    return result;
  end;

Conclusion:
  ALWAYS consider a function for bit-manipulation problems.
  It pays you back handsomely.
--
Jonathan Bromley, Consultant

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Jim, Jonathan,
Thank you!

Jonathan,
Thank you once again for very good conclusion - "ALWAYS consider a
function..."

I was teached VHDL by persons which had next rules:
- do not use function - functions create unnecessary logic compare to
the same inline code
- do not use variables - variables create additional logic compare to
signals
etc...

Now, I am know that it is not true ... but sometimes still programing
like "masochist".

Best regards,
Mariusz

 

[vipinlal]

general uses of concatenation operator is explained here/..
vhdlguru.blogspot.com/2010/03/concatenation-operator-in-vhdl.html