P
Pasacco
Hi
I have problem with using "FOR...GENERATE" of generic component.
My goal is to use "FOR...GENERATE" construct,
in order to instantiate different modules,
depending on condition.
"Exercise1" below works fine.
"Exercise2"-style of construct below does not work.
Question is that
Does VHDL support "Exercise2" style of construct?
If yes, could anyone point out where I can find some examples?
----------------------------------------------------------------
-- Exercise1 : Homogeneous modules
---------------------------------------------------------------
-- MAX : maximum number of instantiated components
CTRL : for i in 0 to MAX-1 generate
Module : Logic_Module
port map(
CLK => CLK, -- clock
RST => RST, -- reset
IN1_i => IN1(i), -- input port
OUT1_o => OUT1(i) ); -- output port
end generate CTRL;
---------------------------------------------------------------
----------------------------------------------------------------
-- Exercise2: Trying to optimize heterogenous modules
-- Temp : integer type signal
---------------------------------------------------------------
CTRL : for i in 0 to MAX-1 generate
if Temp(i) = 0 then --- In this condition, instantiate Logic_ModuleA
ModuleA : Logic_ModuleA
port map(
CLK => CLK,
RST => RST,
IN1_i => IN1(i),
OUT1_o => OUT1(i) );
else --- In this condition, instantiate Logic_ModuleB
ModuleB : Logic_ModuleB
port map(
CLK => CLK,
RST => RST,
IN1_i => IN1(i),
OUT1_o => OUT1(i) );
end generate CTRL;
---------------------------------------------------------------
I have problem with using "FOR...GENERATE" of generic component.
My goal is to use "FOR...GENERATE" construct,
in order to instantiate different modules,
depending on condition.
"Exercise1" below works fine.
"Exercise2"-style of construct below does not work.
Question is that
Does VHDL support "Exercise2" style of construct?
If yes, could anyone point out where I can find some examples?
----------------------------------------------------------------
-- Exercise1 : Homogeneous modules
---------------------------------------------------------------
-- MAX : maximum number of instantiated components
CTRL : for i in 0 to MAX-1 generate
Module : Logic_Module
port map(
CLK => CLK, -- clock
RST => RST, -- reset
IN1_i => IN1(i), -- input port
OUT1_o => OUT1(i) ); -- output port
end generate CTRL;
---------------------------------------------------------------
----------------------------------------------------------------
-- Exercise2: Trying to optimize heterogenous modules
-- Temp : integer type signal
---------------------------------------------------------------
CTRL : for i in 0 to MAX-1 generate
if Temp(i) = 0 then --- In this condition, instantiate Logic_ModuleA
ModuleA : Logic_ModuleA
port map(
CLK => CLK,
RST => RST,
IN1_i => IN1(i),
OUT1_o => OUT1(i) );
else --- In this condition, instantiate Logic_ModuleB
ModuleB : Logic_ModuleB
port map(
CLK => CLK,
RST => RST,
IN1_i => IN1(i),
OUT1_o => OUT1(i) );
end generate CTRL;
---------------------------------------------------------------