Hi,
I have a when-else conditional assignment which contains some don't care values Code is simplified as bellow;
en2 <= '1' when SIG = "010-" else
'1' when SIG ="---1" else
'0';
However, in simulation, en2 only goes high if SIG actually equals "010-" or "---1" as opposed to considering the "-" values as don't cares, the same is true for using "X".
I'm using isim from Xilinx, could anyone tell me if this is a isim thing specifically or if there's another way of coding such that the simulator treats these as real don't care states?
I can imagine that the code would synthesis fine to behave as i wish but am obviously concerned that the simulator doesn't translate it as such?
Much thanks
I have a when-else conditional assignment which contains some don't care values Code is simplified as bellow;
en2 <= '1' when SIG = "010-" else
'1' when SIG ="---1" else
'0';
However, in simulation, en2 only goes high if SIG actually equals "010-" or "---1" as opposed to considering the "-" values as don't cares, the same is true for using "X".
I'm using isim from Xilinx, could anyone tell me if this is a isim thing specifically or if there's another way of coding such that the simulator treats these as real don't care states?
I can imagine that the code would synthesis fine to behave as i wish but am obviously concerned that the simulator doesn't translate it as such?
Much thanks