configuration problem

[Olaf]

Hi,

my VHDL compiler gives the following error message:

** Error: TB_gray_counter.vhd(125): (vcom-1002) Generic 'size' in
component 'gray_counter' does not exist in entity 'gray_counter'.
** Error: TB_gray_counter.vhd(125): (vcom-1002) Generic 'reset_active'
in component 'gray_counter' does not exist in entity 'gray_counter'.

I've no idea what he want - I'm helpless Maybe I'm blind?

Attached the relevant code.

Thanks
Olaf

-- vmap work design_library

entity gray_counter is
generic (
SIZE : Positive range 2 to integer'high := 4;
RESET_ACTIVE : std_logic := '1');

port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
count : out std_logic_vector(SIZE-1 downto 0));
end;

architecture rtl of gray_counter is ....

-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library design_library; -- the DUT
library test_library; -- TB stuff, like clocks etc.

entity TB_gray_counter is
end entity;

architecture behavioral of TB_gray_counter is
-- component generics
constant WIDTH : integer := 4;
constant RESET_ACTIVE : std_logic := '1';
-- all component port signals and other signals
signal dut_clk : std_logic;
signal dut_reset : std_logic;
signal enable : std_logic;
signal gray_count : std_logic_vector(WIDTH-1 downto 0);
signal dec_count : std_logic_vector(gray_count'range);

....
-- DUT
component gray_counter is
generic (
SIZE : Positive range 2 to Integer'high;
RESET_ACTIVE : std_logic);
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
count : out std_logic_vector(SIZE-1 downto 0));
end component gray_counter;
begin
....
DUT: gray_counter
generic map (
SIZE => WIDTH,
RESET_ACTIVE => RESET_ACTIVE)
port map (
clk => dut_clk,
reset => dut_reset,
enable => enable,
count => gray_count);

end architecture;


configuration TBCfg_behavioral of TB_gray_counter is
for behavioral
for DUT : gray_counter
use entity design_library.gray_counter(rtl);
end for; -- XXX line 125
end for;
end configuration;

configuration TBCfg_synthesis of TB_gray_counter is
for behavioral
for DUT : gray_counter
use entity design_library.gray_counter(synthesis);
end for;
end for;
end configuration;


If I write:

configuration TBCfg_behavioral of TB_gray_counter is
for behavioral
for DUT : gray_counter
use entity design_library.gray_counter(rtl)
generic map (
SIZE => 4, -- XXX line 126
RESET_ACTIVE => '1');
end for;
end for;
end configuration;

I've got:
** Error: TB_gray_counter.vhd(126): (vcom-1136) Unknown identifier "size".
** Error: TB_gray_counter.vhd(127): (vcom-1136) Unknown identifier
"reset_active".

 

[Andy]

Hi,

my VHDL compiler gives the following error message:

** Error: TB_gray_counter.vhd(125): (vcom-1002) Generic 'size' in
component 'gray_counter' does not exist in entity 'gray_counter'.
** Error: TB_gray_counter.vhd(125): (vcom-1002) Generic 'reset_active'
in component 'gray_counter' does not exist in entity 'gray_counter'.

I've no idea what he want - I'm helpless Maybe I'm blind?

Attached the relevant code.

Thanks
Olaf

-- vmap work design_library

entity gray_counter is
generic (
SIZE : Positive range 2 to integer'high := 4;
RESET_ACTIVE : std_logic := '1');

port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
count : out std_logic_vector(SIZE-1 downto 0));
end;

architecture rtl of gray_counter is ....

-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library design_library; -- the DUT
library test_library; -- TB stuff, like clocks etc.

entity TB_gray_counter is
end entity;

architecture behavioral of TB_gray_counter is
-- component generics
constant WIDTH : integer := 4;
constant RESET_ACTIVE : std_logic := '1';
-- all component port signals and other signals
signal dut_clk : std_logic;
signal dut_reset : std_logic;
signal enable : std_logic;
signal gray_count : std_logic_vector(WIDTH-1 downto 0);
signal dec_count : std_logic_vector(gray_count'range);

....
-- DUT
component gray_counter is
generic (
SIZE : Positive range 2 to Integer'high;
RESET_ACTIVE : std_logic);
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
count : out std_logic_vector(SIZE-1 downto 0));
end component gray_counter;
begin
....
DUT: gray_counter
generic map (
SIZE => WIDTH,
RESET_ACTIVE => RESET_ACTIVE)
port map (
clk => dut_clk,
reset => dut_reset,
enable => enable,
count => gray_count);

end architecture;

configuration TBCfg_behavioral of TB_gray_counter is
for behavioral
for DUT : gray_counter
use entity design_library.gray_counter(rtl);
end for; -- XXX line 125
end for;
end configuration;

configuration TBCfg_synthesis of TB_gray_counter is
for behavioral
for DUT : gray_counter
use entity design_library.gray_counter(synthesis);
end for;
end for;
end configuration;

If I write:

configuration TBCfg_behavioral of TB_gray_counter is
for behavioral
for DUT : gray_counter
use entity design_library.gray_counter(rtl)
generic map (
SIZE => 4, -- XXX line 126
RESET_ACTIVE => '1');
end for;
end for;
end configuration;

I've got:
** Error: TB_gray_counter.vhd(126): (vcom-1136) Unknown identifier "size".
** Error: TB_gray_counter.vhd(127): (vcom-1136) Unknown identifier
"reset_active".

The tool probably has an old copy of the entity? Need to recompile
gray_counter & rtl arch?

Save yourself a heap of trouble and don't use components and
configurations unless you need them (i.e. want to change them without
touching the source).

Direct entity instantiations are much easier:

DUT: entity work.gray_counter(rtl)
generic map (...


Andy

 

[Paul Uiterlinden]

Hi,

my VHDL compiler gives the following error message:

** Error: TB_gray_counter.vhd(125): (vcom-1002) Generic 'size' in
component 'gray_counter' does not exist in entity 'gray_counter'.
** Error: TB_gray_counter.vhd(125): (vcom-1002) Generic 'reset_active'
in component 'gray_counter' does not exist in entity 'gray_counter'.

I've no idea what he want - I'm helpless Maybe I'm blind?

Attached the relevant code.

Thanks
Olaf

-- vmap work design_library

Whoa! What is this vmap stuff? Why on earth would you map library work to
directory design_library? I suspect there lies your problem.

I can compile your code correctly (with some small editing, such as
adding "library ieee;" and "use ieee.std_logic_1164.all to gray_counter)
with the following commands:

vlib work
vlib design_library
vcom -work design_library dut.vhd # compile into design_library
vcom tb.vhd # compile into work

I just hate it when people do all kind of fancy remapping and renaming stuff
with libraries. All too often, I'm the one to sort it out and clean up the
mess.

Of course, vmap is needed if the directory is located elsewhere. But still,
I stick to the rule

vmap <name> some/path/<name>

So a library <name> always is located in a directory called <name>.

Or better still: in a directory called <name>/mti_<version>, to be able to
support different versions of MTI concurrently.

 

[Olaf]

thanks for all answers. I heed the hint concerning the library

Anyway, the error was related to the synthesis model created by the post
synthesis vhdl model of xst where the entity creation was turned on (is
off for now) - stupid failure.

Thanks
Olaf