Hi.
I've got 2 blocks
first block has output:
out : std_logic_vector[7 downto 0]
and input of the second block:
in: std_logic_vector[15 downto 0]
I want to connect out to in. For example, first 4 bits of in are '0000', next 8 <= out, and the last are also '0000'.
Do I have to implement extra block to do it or there is simplier way?
I've got 2 blocks
first block has output:
out : std_logic_vector[7 downto 0]
and input of the second block:
in: std_logic_vector[15 downto 0]
I want to connect out to in. For example, first 4 bits of in are '0000', next 8 <= out, and the last are also '0000'.
Do I have to implement extra block to do it or there is simplier way?