Constrained-random verification.

[Slawek Grabowski]

Hello,
I am not familiar with the latest revisions of VHDL standard but I am
interested in
constrained-random verification capabilities available in VHDL.
Does VHDL200x support constrained-random verification?
Is it possible to generate data structures like records with constrained
random values ?
Otherwise, SpecMan e or SystemVerilog must be used to implement such kind of
testbenches?

Best Regards,
Slawek Grabowski

 

[Hans]

Hello,
I am not familiar with the latest revisions of VHDL standard but I am
interested in
constrained-random verification capabilities available in VHDL.
Does VHDL200x support constrained-random verification?

It is not build into the language as is the case with SystemVerilog/SystemC
but you can create your own CR data generators and feed that into a record.
It is just a bit of extra work and won't be as flexible as say SystemC but
should be doable. If you go down this route then make sure you understand
functional verification, i.e. you need something (assert, OVL, PSL etc) to
detect that your system is responding OK to your random stimuli unless you
enjoy staring at lots of waveforms

Hans
www.ht-lab.com

 

[Slawek Grabowski]

Thanks Hans, I have started with SystemC and probably use some assertions.
BTW: SystemC appears to be really slow.
IEEE mentions somewhere in the internet that constrained random verification
will be
added to VHDL in 2007.

Best Regards,
Slawek Grabowski