converting a subtype to unsigned?

[laserbeak43]

Hello,
I've created a subtype:

subtype digit is integer range 0 to 9;

and then used this type to make a signal. Is it possible to convert
this type to unsigned? when i do it, i get errors.

signal h1 : digit;
signal hv1 : unsigned(3 downto 0);
hv1 <= unsigned(h1); --Error (10305): VHDL Type Conversion error at
part1.vhd(75): cannot convert type "digit" to type "UNSIGNED"

thanks,
Malik

 

[Jonathan Bromley]

subtype digit is integer range 0 to 9;
Is it possible to convert
this type to unsigned? when i do it, i get errors.

signal h1       : digit;
signal hv1      : unsigned(3 downto 0);
hv1 <= unsigned(h1);  --Error

You're just using the name of the new type (unsigned)
as if it were a function. That's not really a function;
it's a "type conversion", which works only between
closely related types. For example:

- REAL and any INTEGER subtype are closely related,
because they are simple numeric types
- STD_LOGIC_VECTOR and UNSIGNED are closely related,
because they are both arrays of STD_LOGIC indexed
by INTEGER

But INTEGER and UNSIGNED are not closely related, so
you need a conversion function:

hvl = to_unsigned(hl, hvl'length);

If you get an error for this line, it's because you
are a Very Bad Person and are using std_logic_arith.
Switch to numeric_std before we get angry with you

 

[Jonathan Bromley]

  hvl = to_unsigned(hl, hvl'length);

If you get an error for this line, it's because you
are a Very Bad Person and are using std_logic_arith.
Switch to numeric_std before we get angry with you

Alternatively, of course, it might be because I am a
Very Bad Person who forgot the < in a VHDL signal
assignment. Far too much Verilog recently...

 

[laserbeak43]

Alternatively, of course, it might be because I am a
Very Bad Person who forgot the < in a VHDL signal
assignment.  Far too much Verilog recently...

Well if you're a bad person, I'm sure we'd all like to see you on a
good day.
Thanks a lot for your help.
Malik