Core Generator

[create]

Hello,

I created FIFO by CoreGenerator.

I got this code:



LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.PKG_SRAM.all;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_generator_v4_1_a IS
port (
clk: IN std_logic;
din: IN std_logic_VECTOR(DATA_SIZE_OF_SRAM-1 downto 0);
rd_en: IN std_logic;
rst: IN std_logic;
wr_en: IN std_logic;
--data_count: OUT std_logic_VECTOR(4 downto 0);
dout: OUT std_logic_VECTOR(DATA_SIZE_OF_SRAM-1 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
END fifo_generator_v4_1_a;

ARCHITECTURE fifo_generator_v4_1_a OF fifo_generator_v4_1_a IS
-- synthesis translate_off
component wrapped_fifo_generator_v4_1
port (
clk: IN std_logic;
din: IN std_logic_VECTOR(DATA_SIZE_OF_SRAM-1 downto 0);
rd_en: IN std_logic;
rst: IN std_logic;
wr_en: IN std_logic;
-- data_count: OUT std_logic_VECTOR(4 downto 0);
dout: OUT std_logic_VECTOR(DATA_SIZE_OF_SRAM-1 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
end component;

-- Configuration specification
for all : wrapped_fifo_generator_v4_1 use entity
XilinxCoreLib.fifo_generator_v4_1(behavioral)
generic map(
c_has_int_clk => 0,
c_rd_freq => 1,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 0,
c_din_width => 16,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 0,
c_family => "virtex2p",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 16,
c_rd_depth => 1024,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 10,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 1,
c_rd_pntr_width => 10,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 10,
c_enable_rlocs => 0,
c_wr_pntr_width => 10,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 10,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 1,
c_prog_full_thresh_negate_val => 1021,
c_wr_depth => 1024,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 1022,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "1kx18",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_generator_v4_1
port map (
clk => clk,
din => din,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
-- data_count => data_count,
dout => dout,
empty => empty,
full => full);
-- synthesis translate_on

END fifo_generator_v4_1_a;


But synthezer found nothing I think Library XilinxCoreLib is the problem.
What should I do?

I use Xilinx ISE.

Thanks,
zlotawy

 

[Mike Treseler]

Hello,

I created FIFO by CoreGenerator. ....
But synthesizer found nothing

Core Generators make primitive netlists
not synthesis code.

I think Library XilinxCoreLib is the problem.

I think using a core generator to
make a simple fifo is the problem.
Consider writing your own synthesizable code.
See the block ram fifo here:
http://home.comcast.net/~mike_treseler/

What should I do?

Up to you.
For CoreGenerator see http://www.xilinx.com or
http://groups.google.com/group/comp.arch.fpga
If you want to use synthesis, see above.

-- Mike Treseler

 

[Brian Drummond]

Hello,

I created FIFO by CoreGenerator.

I got this code:



LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.PKG_SRAM.all;
-- synthesis translate_off
-- synthesis translate_on ^^^^^^^^^^^^^^^^^^^^^
ENTITY fifo_generator_v4_1_a IS

END fifo_generator_v4_1_a;

ARCHITECTURE fifo_generator_v4_1_a OF fifo_generator_v4_1_a IS...

-- synthesis translate_off
-- synthesis translate_on ^^^^^^^^^^^^^^^^^^^^^

END fifo_generator_v4_1_a;


But synthezer found nothing

What a surprise...

I think Library XilinxCoreLib is the problem.
What should I do?

Synthesis is then supposed to treat the FIFO as a "black box"; check the
synthesis report for statements that it did.

Core Generator should also have generated a netlist, with an .edn or
..ngo extension. Make sure the downstream tools (Translate/Map/Par) can
find this netlist; Translate should report finding it and including it
in the project.

You can do that by either moving files around (into the ISE project
directory) or setting a "netlist include path" in the Translate
properties (or command line) to point to the files.

Or, as Mike says, forget about Coregen.

- Brian