Correct VHDL?

[mightycatniyander]

Hello,
I want to implement the following C++ code in VHDL

double t1 = u1 * ip1[i1] - u2 * op1[i1];
double t2 = u1 * op1[i1] + u2 * ip1[i1];
ip1[i1] = ip3 - t1;
op1[i1] = ip4 - t2;
ip3 += t1;
ip4 += t2;

i am not sure if this is correct but i have tried and came up with the
following VHDL

entity test is
port( clk : in std_logic;
ip1 : in std_logic_vector(7 downto 0);
op1 : in std_logic_vector(7 downto 0);
ip3 : in std_logic_vector(7 downto 0);
ip4 : in std_logic_vector(7 downto 0);
U1 : in std_logic_vector(7 downto 0);
U2 : in std_logic_vector(7 downto 0);
ip1o : out std_logic_vector(15 downto 0);
op1o : out std_logic_vector(15 downto 0);
ip3o : out std_logic_vector(15 downto 0);
ip4o : out std_logic_vector(15 downto 0));
end test;

architecture Behavioral of test is
signal T1 : std_logic_vector(15 downto 0);
signal T2 : std_logic_vector(15 downto 0);
begin

process(clk)
begin
T1 <= (U1 * ip1) - (U2 * op1);
T2 <= (U1 * op1) + (U2 * ip1);
ip1o <= ip3 - T1;
op1o <= ip4 - T2;
ip3o <= ip3 + T1;
ip4o <= ip4 + T2;
end process;

end Behavioral;

i would really appreciate if some one can tell me is it correct, if
not how can it be implemented correctly in VHDL?

further i want to implement this code in a sort of variable loop, i.e.
depending on the values of the output the length of the loop will
change. For example consider the following c++ code

for (int a=0; a<=100; a++)
{
i1 = i2;
i2 *= 2;
for (int i=i1; i<=k; i++)
{
//some code here;
}
}

could this be implemented in VHDL?

Thanks

 

[JohnDuq]

After a quick glance it looks like it should almost work. Here is what pops out at me:

- You changed t1 and t2 from a double to a 32-bit value, so go through the math and verify you won't run out of bits. Floating point is avaliable in VHDL but I have never used it.

- don't forget your library definitions. You will need some (all?) of thse

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


- you can set up a FOR loop in VHDL check out

http: // www dot vhdl-online dot de / tutorial / englisch / inhalt.htm


There are lots of simulators available. I suggest you run this through a simulator and see what comes out.

John

 

[Mike Treseler]

No, it's not correct.

you're trying to perform arithmetic on std_logic_vectors,
with no libraries linked in. The std_logic_arith library will allow
you to do that, but shouldn't, as it completely throws away any concept
of typing.

Actually it's the the synopsys
std_logic_unsigned and
std_logic_signed packages
that attempt math on std_logic_vectors.
These packages do not play nice with each other
or with the standard comparison operators.

The std_logic_arith package causes less havoc because
it requires the use signed and unsigned types.
Users of the synopsys "verilog subset" rarely employ these.

-- Mike Treseler

 

[JohnDuq]

Ah, I can tell I'm starting to learn enough about this to be dangerous! Is there a good summary anywhere of what each library can and can't do? I'm typically working with Xilinx parts and tools. Does that make a difference or does Xilinx reference standard libraries?

Thanks,

John