CRC calculation

[edi.fraiman]

Hi,

In my design FPGA is between MAC and PHY. I have to change frame
payload and recalculate CRC. I calculate CRC over the destination
address + source address+ length/type +new data+ pad.

I am using Ethereal SW in order capture frame. So I am trying to
calculate CRC on original frame (without changing data) and compare to
what captured by Ethereal.
But it's never same (also even result is inverted and reflected)

Here is VHDL code.
---------------------------------------------------------------------------------------------------
entity crc_gen is
port ( crc : out STD_LOGIC_VECTOR (31 downto 0);
d_in : in STD_LOGIC_VECTOR (3 downto 0);
clk,en,nPOR,MAC_MII_TXEN : in std_logic);
end crc_gen;

architecture Behavioral of crc_gen is
--
signal NewCRC : STD_LOGIC_VECTOR(31 downto 0);
signal OldCRC : STD_LOGIC_VECTOR(31 downto 0);
--
begin
NewCRC(0) <= d_in(0) xor OldCRC(28);
NewCRC(0) <= d_in(0) xor OldCRC(28);
NewCRC(1) <= d_in(1) xor d_in(0) xor OldCRC(28) xor OldCRC(29);
NewCRC(2) <= d_in(2) xor d_in(1) xor d_in(0) xor OldCRC(28) xor
OldCRC(29) xor OldCRC(30);
NewCRC(3) <= d_in(3) xor d_in(2) xor d_in(1) xor OldCRC(29) xor
OldCRC(30) xor OldCRC(31);
NewCRC(4) <= d_in(3) xor d_in(2) xor d_in(0) xor OldCRC(0) xor
OldCRC(28) xor OldCRC(30) xor
OldCRC(31);
NewCRC(5) <= d_in(3) xor d_in(1) xor d_in(0) xor OldCRC(1) xor
OldCRC(28) xor OldCRC(29) xor
OldCRC(31);
NewCRC(6) <= d_in(2) xor d_in(1) xor OldCRC(2) xor OldCRC(29) xor
OldCRC(30);
NewCRC(7) <= d_in(3) xor d_in(2) xor d_in(0) xor OldCRC(3) xor
OldCRC(28) xor OldCRC(30) xor
OldCRC(31);
NewCRC(8) <= d_in(3) xor d_in(1) xor d_in(0) xor OldCRC(4) xor
OldCRC(28) xor OldCRC(29) xor
OldCRC(31);
NewCRC(9) <= d_in(2) xor d_in(1) xor OldCRC(5) xor OldCRC(29) xor
OldCRC(30);
NewCRC(10) <= d_in(3) xor d_in(2) xor d_in(0) xor OldCRC(6) xor
OldCRC(28) xor OldCRC(30) xor
OldCRC(31);
NewCRC(11) <= d_in(3) xor d_in(1) xor d_in(0) xor OldCRC(7) xor
OldCRC(28) xor OldCRC(29) xor
OldCRC(31);
NewCRC(12) <= d_in(2) xor d_in(1) xor d_in(0) xor OldCRC(8) xor
OldCRC(28) xor OldCRC(29) xor
OldCRC(30);
NewCRC(13) <= d_in(3) xor d_in(2) xor d_in(1) xor OldCRC(9) xor
OldCRC(29) xor OldCRC(30) xor
OldCRC(31);
NewCRC(14) <= d_in(3) xor d_in(2) xor OldCRC(10) xor OldCRC(30)
xor OldCRC(31);
NewCRC(15) <= d_in(3) xor OldCRC(11) xor OldCRC(31);
NewCRC(16) <= d_in(0) xor OldCRC(12) xor OldCRC(28);
NewCRC(17) <= d_in(1) xor OldCRC(13) xor OldCRC(29);
NewCRC(18) <= d_in(2) xor OldCRC(14) xor OldCRC(30);
NewCRC(19) <= d_in(3) xor OldCRC(15) xor OldCRC(31);
NewCRC(20) <= OldCRC(16);
NewCRC(21) <= OldCRC(17);
NewCRC(22) <= d_in(0) xor OldCRC(18) xor OldCRC(28);
NewCRC(23) <= d_in(1) xor d_in(0) xor OldCRC(19) xor OldCRC(28)
xor OldCRC(29);
NewCRC(24) <= d_in(2) xor d_in(1) xor OldCRC(20) xor OldCRC(29)
xor OldCRC(30);
NewCRC(25) <= d_in(3) xor d_in(2) xor OldCRC(21) xor OldCRC(30)
xor OldCRC(31);
NewCRC(26) <= d_in(3) xor d_in(0) xor OldCRC(22) xor OldCRC(28)
xor OldCRC(31);
NewCRC(27) <= d_in(1) xor OldCRC(23) xor OldCRC(29);
NewCRC(28) <= d_in(2) xor OldCRC(24) xor OldCRC(30);
NewCRC(29) <= d_in(3) xor OldCRC(25) xor OldCRC(31);
NewCRC(30) <= OldCRC(26);
NewCRC(31) <= OldCRC(27);
--
process (clk)
begin
if rising_edge (clk) then
if (nPOR = '0' or MAC_MII_TXEN = '0') then
OldCRC <= (others => '1');
elsif (en = '1') then
OldCRC <= NewCRC;
else
null;
end if;
end if;
end process;
--
crc <= OldCRC;
--
end Behavioral;
---------------------------------------------

Could somebody help me?

Best regards,
Edi Fraiman

 

[Mike Treseler]

In my design FPGA is between MAC and PHY. I have to change frame
payload and recalculate CRC. I calculate CRC over the destination
address + source address+ length/type +new data+ pad.

I am using Ethereal SW in order capture frame. So I am trying to
calculate CRC on original frame (without changing data) and compare to
what captured by Ethereal.
But it's never same (also even result is inverted and reflected)

There are lots of ways to get this wrong.
Start googling here:
http://groups.google.com/groups/search?q=crc_shift

Here is VHDL code.

I would run a sim and do some debugging
to obtain a specific question to ask here.
Good luck.

-- Mike Treseler

 

[Paul Uiterlinden]

Could somebody help me?

Check out http://www.easics.com/webtools/crctool

Using that, you "just" have to sort out the right bit/byte order and
initialization. Do a simulation with a known good ethernet frame. If
I remember correctly, some known good frames can be found in the IEEE
standard.

 

[Kai Harrekilde-Petersen]

Check out http://www.easics.com/webtools/crctool

Using that, you "just" have to sort out the right bit/byte order and
initialization. Do a simulation with a known good ethernet frame. If
I remember correctly, some known good frames can be found in the IEEE
standard.

Affirmative. There are some in Annex 36A.4 and 36A.5 at least.

Kai

 

[Marcus Harnisch]

But it's never same (also even result is inverted and reflected)

I'd suggest consulting the standard. Things are a bit confusing,
indeed.

,----[ IEEE 802.3, 2000 Edition, p41 ]
| The bits of the CRC are thus transmitted in the order x^31,
| x^30,...,x^1,x^0.
`----

Which incidentially is the opposite order of all other data in a
frame.

-- Marcus
note that "property" can also be used as syntaxtic sugar to reference
a property, breaking the clean design of verilog; [...]

-- Michael McNamara
(http://www.veripool.com/verilog-mode_news.html)