dac model ad7304 gives

[aem]

I got this model off your website, created the FMF lib and then compiled gen_utils.vhd and conversions.vhd sucessfully in this lib. I then tried to compile the ad7304 model. I assumed these models worked but I get these errors about the ports:

Model Technology ModelSim SE vcom 6.2d Compiler 2006.10 Oct 16 2006
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package vital_timing
-- Loading package vital_primitives
-- Loading package gen_utils
-- Loading package conversions
-- Compiling entity ad7304
** Error: C:/my/path/ad7304.vhd(76): Type mark in declaration of port 'vrefa' must be std_logic_vector or std_ulogic.
(1076.4 section 4.3.1)
** Error: C:/my/path/ad7304.vhd(76): Scalar port declaration cannot contain a range constraint.
(1076.4 section 4.3.1)
** Error: C:/my/path/ad7304.vhd(77): Type mark in declaration of port 'vrefb' must be std_logic_vector or std_ulogic.
(1076.4 section 4.3.1)
** Error: C:/my/path/ad7304.vhd(77): Scalar port declaration cannot contain a range constraint.
(1076.4 section 4.3.1)
** Error: C:/my/path/ad7304.vhd(78): Type mark in declaration of port 'vrefc' must be std_logic_vector or std_ulogic.
(1076.4 section 4.3.1)
** Error: C:/my/path/ad7304.vhd(78): Scalar port declaration cannot contain a range constraint.
(1076.4 section 4.3.1)
** Error: C:/my/path/ad7304.vhd(79): Type mark in declaration of port 'vrefd' must be std_logic_vector or std_ulogic.
(1076.4 section 4.3.1)
** Error: C:/my/path/ad7304.vhd(79): Scalar port declaration cannot contain a range constraint.
(1076.4 section 4.3.1)
** Error: C:/my/path/ad7304.vhd(80): Type mark in declaration of port 'vouta' must be std_logic_vector or std_ulogic.
(1076.4 section 4.3.1)
** Error: C:/my/path/ad7304.vhd(80): Scalar port declaration cannot contain a range constraint.
(1076.4 section 4.3.1)
** Error: C:/my/path/ad7304.vhd(81): Type mark in declaration of port 'voutb' must be std_logic_vector or std_ulogic.
(1076.4 section 4.3.1)
** Error: C:/my/path/ad7304.vhd(81): Scalar port declaration cannot contain a range constraint.
(1076.4 section 4.3.1)
** Error: C:/my/path/ad7304.vhd(82): Type mark in declaration of port 'voutc' must be std_logic_vector or std_ulogic.
(1076.4 section 4.3.1)
** Error: C:/my/path/ad7304.vhd(82): Scalar port declaration cannot contain a range constraint.
(1076.4 section 4.3.1)
** Error: C:/my/path/ad7304.vhd(83): Type mark in declaration of port 'voutd' must be std_logic_vector or std_ulogic.
(1076.4 section 4.3.1)
** Error: C:/my/path/ad7304.vhd(83): Scalar port declaration cannot contain a range constraint.
(1076.4 section 4.3.1)
** Error: C:/my/path/ad7304.vhd(92): VHDL Compiler exiting

 

[aem]

I lied. The model was from http://www.freemodelfoundry.com/fmf_VHDL_models.html not from this website and it's of a DAC. AD7304.

Sorry.

 

[aem]

I'll answer my own question for others if they run into this issue (don't know how to remove/delete thread).
There is a note in the code that says "-- This model must be compiled without VITAL compliance checking" but I wasnt' sure what that meant intially. anyway you need the -novitalcheck

vcom -novitalcheck C:/my/path/ad7304.vhd