Display test on Active-VHDL

[joao12345678joao]

Hi guys! im new here on the forum, and i'm using active-VHDL compiler. I did a Display but I dont know how can I simulate it. I'll post my code and, please, If somebody knows, tell me how can I simulate it!
If somebody finds any error in the code, please, tell me xD

Hugss!


library IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.std_logic_unsigned.ALL;

entity Input is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : out STD_LOGIC_VECTOR(6 downto 0)
);
end Input;

--}} End of automatically maintained section

architecture Display of Input is
begin
process(a)
begin
CASE a is
when "0000" => b <="1111110";
when "0001" => b <="0110000";
when "0010" => b <="1101101";
when "0011" => b <="1111001";
when "0100" => b <="0110011";
when "0101" => b <="1011011";
when "0110" => b <="1011111";
when "0111" => b <="1110000";
when "1000" => b <="1111111";
when "1001" => b <="1110011";
when others => b <="0000001";
end CASE;
end process;

-- enter your statements here --
end Display;

 

[eliascm]

In Active-HDL, click on Help/On-line Documentation/Tutorials/HDL Entry and Simulation Tutorial

This will get you started. If you still have questions after working this tutorial, come back to this forum and post the question(s).

Charles

 

[joao12345678joao]

Thanks, Charles. It's a usefull help that I didn't find before.
Its being hard begin with VHDL. I'm trying to find some exemples inside internet to have a work base, but few sites are good for this. If I have any problem, i'll come here ask you haha

Hugs