Hello everyone,
At the moment I am doing a project which follows another project done by someone else. The code he left behind surprises me sometimes, or at least very strange. The next code is one of his.
The first part (entity) with the many <, = and > is for me quite strange (and the .mine and .r10 too). I can't understand what he is trying to do so I hope some of you know.
Greets,
Jan
At the moment I am doing a project which follows another project done by someone else. The code he left behind surprises me sometimes, or at least very strange. The next code is one of his.
Code:
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--THE DETECTED BITS FROM THE BIT DETECTOR ARE PUT IN--
--A SHIFT REGISTER. EVERY TIME THE DATA 000001 --
--PASSES, THE PREAMBLE BECOMES VALID FOR A PERIOD --
--OF 29 BITS (36 BITS MINUS THE PREAMBLE AND THE --
--LAST END MARKER) --
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
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ENTITY Preamble_Detector IS
<<<<<<< .mine
PORT ( serial_in: IN STD_LOGIC;
=======
PORT ( serial_in,
>>>>>>> .r10
bit_in: IN STD_LOGIC;
bit_out: OUT STD_LOGIC;
preamble_valid: BUFFER STD_LOGIC
);
END Preamble_Detector;
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ARCHITECTURE behaviour OF Preamble_Detector IS
SIGNAL shiftreg : STD_LOGIC_VECTOR ( 4 DOWNTO 0);
BEGIN
PROCESS (serial_in, bit_in)
VARIABLE counter : INTEGER RANGE 0 TO 28 := 28;
BEGIN
----SHIFT REGISTER----
IF (serial_in'EVENT AND serial_in='1') THEN
shiftreg <= bit_in & shiftreg (shiftreg'LEFT DOWNTO 1); --PUTS THE DETECTED BITS IN A SHIFTREGISTER
END IF;
----CHECK FOR PREAMBLE----
IF (shiftreg="00000" AND bit_in='1') THEN
counter := 0;
IF (serial_in'EVENT AND serial_in='1') THEN
preamble_valid <= '1'; --MAKES THE PREAMBLE VALID ON THE NEXT SERIAL_IN EVENT
bit_out <= bit_in; --IF THE REGISTER CONTAINS 5 0'S AND THE CURRENT INPUT IS
END IF; --'1' (PREAMBLE=000001) AND PUTS THE FIRST BIT AFTER THE
----PASS BITS IF PREAMBLE IS VALID---- --PREAMBLE ON THE OUTPUT
ELSIF (counter < 28) THEN
preamble_valid <= '0';
bit_out <= bit_in; --PASSES THE BITS AS LONG AS PREAMBLE IS VALID
IF (serial_in'EVENT AND serial_in='1') THEN
counter := counter + 1; --RAISES THE COUNTER AS LONG AS DATA HAS TO BE CLOCKED IN
END IF;
ELSIF (counter=28) THEN
bit_out <= '0'; --RESETS THE PREAMBLE_VALID AND COUNTER AND STOPS PASSING THE
END IF; --BITS AT THE END OF THE DATA
END PROCESS;
END behaviour;
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Greets,
Jan