Emacs VHDL-mode Compiler Setup

[M. Norton]

Hi,

I've been teaching myself Emacs going along for these past few
projects but haven't done much more than the essential editing and
using some of the VHDL mode tools like the declaration copying and
beautification. I thought today I might try to get the compiler
portion working. It's close, but not quite there and I thought I
might see if someone else knows the emacs trick for it.

I have setup my project as follows below. The trouble seems to be the
library name. According to the help text below the settings, \1
inserts the library name and \2 inserts the default options. Well as
can be seen, the Library directory is located someplace other than as
an offshoot of the source directory. How can I make it insert the
library path and then the library name? With the settings shown
below, it gives a compiler command of "vcom -93 -work work foo.vhd".
What I need is "vcom -93 -work /path/to/library/directory/work
foo.vhd".

Vhdl Project Alist: Hide
INS DEL Project:
Name : lcdc_fpga
Title : LCD Controller FPGA Verification
Default directory: ~/lcdc_fpga/
Sources :
INS DEL -r verify/tb/
INS
Exclude regexp :
Compile options :
INS DEL Compiler:
Compiler name: Value Menu ModelSim
Compile options: -93 -work \1
Make options : -f \1 top_level
Exceptions :
INS
INS
Compile directory: verify/tb/
Library name : work
Library directory: verify/sim/
Makefile name : Makefile_\2
Description: (type `C-j' for newline)

Thanks for any Emacs guru help out there. I did some group and google
searches but didn't seem to turn up anything useful.

Mark

 

[M. Norton]

Well I may have solved it by accident. I noticed in the VHDL menu
that the little radio box by the project I had created was not
checked. I clicked it, and then also selected Set Default Project.
Now when I use the compiler it seems to be using the options I
selected.

Useful tool, just requires some luck ;-)

Mark

 

[Mike Treseler]

Well I may have solved it by accident. I noticed in the VHDL menu
that the little radio box by the project I had created was not
checked. I clicked it, and then also selected Set Default Project.
Now when I use the compiler it seems to be using the options I
selected.

Yes. If the project isn't set, it uses the current directory
instead of the specified settings.
I can do that on the menu VHDL, project ...
or on the speedbar.

Useful tool, just requires some luck ;-)

Or trial and error.
Make sure you read everything in VHDL, documentation, ...

-- Mike Treseler